Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49829

1

T8

14

T30

332

T31

316

auto[1]

18289

1

T5

2

T6

122

T14

1

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49604

1

T5

2

T6

122

T8

4

auto[1]

18514

1

T8

10

T30

146

T31

100

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	35110	1			T5	2		T6	66		T8	4
others[1]	5774	1			T6	10		T8	1		T26	37
others[2]	5665	1			T6	13		T8	4		T26	27
others[3]	6439	1			T6	10		T26	36		T29	56
interest[1]	3809	1			T6	4		T8	3		T26	24
interest[4]	22984	1			T5	2		T6	44		T8	3
interest[64]	11321	1			T6	19		T8	2		T26	57

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	16031	1			T8	2		T30	97		T31	117
auto[0]	auto[0]	others[1]	2647	1			T30	11		T31	19		T32	35
auto[0]	auto[0]	others[2]	2669	1			T30	15		T31	15		T32	29
auto[0]	auto[0]	others[3]	2974	1			T30	23		T31	16		T32	28
auto[0]	auto[0]	interest[1]	1753	1			T8	1		T30	14		T31	15
auto[0]	auto[0]	interest[4]	10442	1			T8	1		T30	74		T31	73
auto[0]	auto[0]	interest[64]	5241	1			T8	1		T30	26		T31	34
auto[0]	auto[1]	others[0]	9559	1			T5	2		T6	66		T14	1
auto[0]	auto[1]	others[1]	1545	1			T6	10		T26	37		T29	33
auto[0]	auto[1]	others[2]	1454	1			T6	13		T26	27		T29	41
auto[0]	auto[1]	others[3]	1755	1			T6	10		T26	36		T29	56
auto[0]	auto[1]	interest[1]	1013	1			T6	4		T26	24		T29	14
auto[0]	auto[1]	interest[4]	6352	1			T5	2		T6	44		T14	1
auto[0]	auto[1]	interest[64]	2963	1			T6	19		T26	57		T29	69
auto[1]	auto[0]	others[0]	9520	1			T8	2		T30	84		T31	46
auto[1]	auto[0]	others[1]	1582	1			T8	1		T30	8		T31	9
auto[1]	auto[0]	others[2]	1542	1			T8	4		T30	16		T31	13
auto[1]	auto[0]	others[3]	1710	1			T30	12		T31	5		T32	15
auto[1]	auto[0]	interest[1]	1043	1			T8	2		T30	8		T31	4
auto[1]	auto[0]	interest[4]	6190	1			T8	2		T30	57		T31	26
auto[1]	auto[0]	interest[64]	3117	1			T8	1		T30	18		T31	23

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal