Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2557197	1			T1	1		T2	1		T3	1
all_values[1]	2557197	1			T1	1		T2	1		T3	1
all_values[2]	2557197	1			T1	1		T2	1		T3	1
all_values[3]	2557197	1			T1	1		T2	1		T3	1
all_values[4]	2557197	1			T1	1		T2	1		T3	1
all_values[5]	2557197	1			T1	1		T2	1		T3	1
all_values[6]	2557197	1			T1	1		T2	1		T3	1
all_values[7]	2557197	1			T1	1		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19847419

1

T1

8

T2

8

T3

8

auto[1]

610157

1

T9

81

T20

43

T97

47

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20433095

1

T1

8

T2

8

T3

8

auto[1]

24481

1

T9

57

T20

52

T97

41

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2519353	1			T1	1		T2	1		T3	1
all_values[0]	auto[0]	auto[1]	10945	1			T9	3		T20	4		T97	1
all_values[0]	auto[1]	auto[0]	26442	1			T9	6		T20	8		T97	3
all_values[0]	auto[1]	auto[1]	457	1			T9	2		T97	2		T32	174
all_values[1]	auto[0]	auto[0]	2431871	1			T1	1		T2	1		T3	1
all_values[1]	auto[0]	auto[1]	7196	1			T9	4		T20	4		T97	1
all_values[1]	auto[1]	auto[0]	117734	1			T9	5		T20	4		T97	6
all_values[1]	auto[1]	auto[1]	396	1			T9	7		T20	1		T97	1
all_values[2]	auto[0]	auto[0]	2441519	1			T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	3064	1			T9	5		T20	3		T97	2
all_values[2]	auto[1]	auto[0]	112300	1			T9	4		T20	3		T97	3
all_values[2]	auto[1]	auto[1]	314	1			T9	2		T20	3		T97	1
all_values[3]	auto[0]	auto[0]	2444790	1			T1	1		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	240	1			T9	5		T20	4		T97	5
all_values[3]	auto[1]	auto[0]	111931	1			T9	9		T97	3		T32	10
all_values[3]	auto[1]	auto[1]	236	1			T9	1		T20	4		T97	3
all_values[4]	auto[0]	auto[0]	2521438	1			T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	216	1			T9	5		T20	6		T97	4
all_values[4]	auto[1]	auto[0]	35321	1			T9	8		T20	5		T97	1
all_values[4]	auto[1]	auto[1]	222	1			T9	3		T20	2		T97	4
all_values[5]	auto[0]	auto[0]	2502528	1			T1	1		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	196	1			T9	3		T20	5		T97	2
all_values[5]	auto[1]	auto[0]	54283	1			T9	10		T97	6		T32	7
all_values[5]	auto[1]	auto[1]	190	1			T9	2		T97	4		T32	1
all_values[6]	auto[0]	auto[0]	2482852	1			T1	1		T2	1		T3	1
all_values[6]	auto[0]	auto[1]	180	1			T20	7		T97	3		T32	7
all_values[6]	auto[1]	auto[0]	73938	1			T9	11		T20	2		T97	3
all_values[6]	auto[1]	auto[1]	227	1			T9	6		T20	2		T97	2
all_values[7]	auto[0]	auto[0]	2480814	1			T1	1		T2	1		T3	1
all_values[7]	auto[0]	auto[1]	217	1			T9	7		T20	3		T97	4
all_values[7]	auto[1]	auto[0]	75981	1			T9	3		T20	5		T97	3
all_values[7]	auto[1]	auto[1]	185	1			T9	2		T20	4		T97	2