Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.03 98.38 93.99 98.62 89.36 97.19 95.45 99.21


Total tests in report: 1131
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
64.61 64.61 92.39 92.39 80.59 80.59 82.78 82.78 28.89 28.89 89.14 89.14 71.83 71.83 6.68 6.68 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_intercept.1260919688
73.93 9.32 95.67 3.28 86.44 5.86 85.93 3.15 51.11 22.22 93.47 4.33 79.80 7.97 25.10 18.42 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_and_tpm.136986722
81.18 7.25 97.28 1.61 89.43 2.98 86.32 0.39 80.00 28.89 95.72 2.25 84.50 4.69 35.05 9.95 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_all.3924908221
84.18 2.99 97.76 0.48 90.55 1.12 88.68 2.36 82.22 2.22 96.28 0.56 84.64 0.14 49.11 14.06 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_stress_all.2213288240
85.93 1.75 97.76 0.00 90.64 0.09 88.68 0.00 82.22 0.00 96.28 0.00 84.78 0.14 61.14 12.03 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_and_tpm.1459788156
87.58 1.65 97.78 0.02 90.77 0.14 89.67 0.98 82.22 0.00 96.31 0.03 93.31 8.53 62.97 1.83 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_intg_err.138644655
88.97 1.39 97.87 0.09 90.98 0.21 89.67 0.00 86.67 4.44 96.50 0.19 93.31 0.00 67.77 4.80 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_all.166422023
90.16 1.19 98.00 0.13 91.15 0.16 92.03 2.36 91.11 4.44 96.64 0.14 93.31 0.00 68.86 1.09 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_upload.1633536045
90.86 0.70 98.10 0.10 91.15 0.00 96.75 4.72 91.11 0.00 96.70 0.07 93.31 0.00 68.86 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_ram_cfg.192515123
91.52 0.66 98.10 0.00 91.15 0.00 96.75 0.00 91.11 0.00 96.70 0.00 93.31 0.00 73.51 4.65 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_stress_all.1483561464
92.11 0.59 98.10 0.00 91.15 0.00 96.75 0.00 91.11 0.00 96.70 0.00 93.31 0.00 77.67 4.16 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_and_tpm_min_idle.78572219
92.58 0.47 98.11 0.01 91.18 0.04 96.75 0.00 93.33 2.22 96.72 0.02 93.31 0.00 78.66 0.99 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_all.4129878499
92.98 0.40 98.14 0.03 91.22 0.04 96.75 0.00 93.33 0.00 96.79 0.07 93.31 0.00 81.34 2.67 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_all.4214921391
93.33 0.34 98.14 0.00 91.22 0.00 96.75 0.00 93.33 0.00 96.79 0.00 93.60 0.28 83.47 2.13 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_stress_all.1111945834
93.66 0.33 98.25 0.11 92.65 1.43 96.75 0.00 93.33 0.00 96.97 0.19 94.17 0.57 83.47 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_read_buffer_direct.3126609265
93.96 0.31 98.25 0.00 93.48 0.83 97.15 0.39 93.33 0.00 97.01 0.03 94.31 0.14 84.21 0.74 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.3082572399
94.21 0.25 98.25 0.00 93.52 0.04 97.15 0.00 93.33 0.00 97.02 0.02 94.31 0.00 85.89 1.68 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_mode_ignore_cmds.1587942947
94.46 0.25 98.28 0.03 93.56 0.04 97.15 0.00 93.33 0.00 97.09 0.07 94.31 0.00 87.48 1.58 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_and_tpm.1761053166
94.70 0.24 98.28 0.00 93.58 0.02 98.43 1.28 93.33 0.00 97.09 0.00 94.45 0.14 87.72 0.25 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_sec_cm.2085254745
94.85 0.16 98.28 0.00 93.58 0.00 98.43 0.00 93.33 0.00 97.09 0.00 94.45 0.00 88.81 1.09 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_and_tpm_min_idle.3101736815
95.00 0.15 98.30 0.02 93.61 0.02 98.43 0.00 93.33 0.00 97.14 0.05 94.45 0.00 89.75 0.94 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_and_tpm_min_idle.2169651075
95.14 0.13 98.30 0.00 93.61 0.00 98.43 0.00 93.33 0.00 97.14 0.00 94.45 0.00 90.69 0.94 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_and_tpm.3602841244
95.26 0.13 98.30 0.00 93.61 0.00 98.43 0.00 93.33 0.00 97.14 0.00 94.45 0.00 91.58 0.89 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_all.2762282885
95.39 0.13 98.30 0.00 93.63 0.02 98.43 0.00 93.33 0.00 97.14 0.00 95.31 0.85 91.58 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3226488544
95.51 0.12 98.30 0.00 93.63 0.00 98.43 0.00 93.33 0.00 97.14 0.00 95.31 0.00 92.43 0.84 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_all.600732719
95.62 0.11 98.30 0.00 93.63 0.00 98.43 0.00 93.33 0.00 97.14 0.00 95.45 0.14 93.07 0.64 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_stress_all.1140190666
95.70 0.08 98.30 0.00 93.63 0.00 98.43 0.00 93.33 0.00 97.14 0.00 95.45 0.00 93.61 0.54 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_stress_all.3382848108
95.78 0.08 98.33 0.03 93.68 0.05 98.43 0.00 93.33 0.00 97.16 0.02 95.45 0.00 94.06 0.45 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_pass_addr_payload_swap.4229598700
95.84 0.06 98.33 0.00 93.68 0.00 98.43 0.00 93.33 0.00 97.16 0.00 95.45 0.00 94.50 0.45 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_mode_ignore_cmds.965721216
95.90 0.06 98.33 0.00 93.78 0.10 98.43 0.00 93.33 0.00 97.18 0.02 95.45 0.00 94.80 0.30 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_mode_ignore_cmds.1346537868
95.96 0.06 98.33 0.00 93.78 0.00 98.43 0.00 93.33 0.00 97.18 0.00 95.45 0.00 95.20 0.40 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_read_hw_reg.3879467636
96.01 0.06 98.33 0.00 93.78 0.00 98.43 0.00 93.33 0.00 97.18 0.00 95.45 0.00 95.59 0.40 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_all.665717418
96.06 0.05 98.33 0.00 93.78 0.00 98.43 0.00 93.33 0.00 97.18 0.00 95.45 0.00 95.94 0.35 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_intg_err.773998476
96.10 0.04 98.33 0.00 93.78 0.00 98.43 0.00 93.33 0.00 97.18 0.00 95.45 0.00 96.24 0.30 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_all.3202585506
96.14 0.04 98.36 0.03 93.82 0.04 98.62 0.20 93.33 0.00 97.18 0.00 95.45 0.00 96.24 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_alert_test.1901438036
96.18 0.04 98.36 0.00 93.82 0.00 98.62 0.00 93.33 0.00 97.18 0.00 95.45 0.00 96.49 0.25 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_and_tpm.1366674036
96.21 0.04 98.36 0.00 93.82 0.00 98.62 0.00 93.33 0.00 97.18 0.00 95.45 0.00 96.73 0.25 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_and_tpm.234415553
96.25 0.04 98.36 0.00 93.82 0.00 98.62 0.00 93.33 0.00 97.18 0.00 95.45 0.00 96.98 0.25 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_mode.3742632769
96.28 0.03 98.36 0.00 93.82 0.00 98.62 0.00 93.33 0.00 97.18 0.00 95.45 0.00 97.18 0.20 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_cfg_cmd.650749050
96.30 0.03 98.36 0.00 93.82 0.00 98.62 0.00 93.33 0.00 97.18 0.00 95.45 0.00 97.38 0.20 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_all.1155187597
96.33 0.02 98.36 0.00 93.83 0.01 98.62 0.00 93.33 0.00 97.18 0.00 95.45 0.00 97.52 0.15 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_and_tpm_min_idle.1910476688
96.35 0.02 98.36 0.00 93.93 0.10 98.62 0.00 93.33 0.00 97.18 0.00 95.45 0.00 97.57 0.05 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_errors.67263466
96.37 0.02 98.36 0.00 93.93 0.00 98.62 0.00 93.33 0.00 97.18 0.00 95.45 0.00 97.72 0.15 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_intg_err.4021761586
96.39 0.02 98.36 0.00 93.93 0.00 98.62 0.00 93.33 0.00 97.18 0.00 95.45 0.00 97.87 0.15 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_mode_ignore_cmds.1236263214
96.41 0.02 98.36 0.00 93.93 0.00 98.62 0.00 93.33 0.00 97.18 0.00 95.45 0.00 98.02 0.15 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_and_tpm_min_idle.448217669
96.43 0.02 98.36 0.00 93.93 0.00 98.62 0.00 93.33 0.00 97.18 0.00 95.45 0.00 98.17 0.15 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_and_tpm_min_idle.4154878350
96.45 0.02 98.36 0.01 93.93 0.00 98.62 0.00 93.33 0.00 97.19 0.02 95.45 0.00 98.27 0.10 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_mailbox.1802134829
96.47 0.02 98.36 0.00 93.94 0.01 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 98.37 0.10 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_all.3052482652
96.48 0.01 98.36 0.00 93.94 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 98.47 0.10 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_stress_all.51023075
96.50 0.01 98.36 0.00 93.94 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 98.56 0.10 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_mode_ignore_cmds.2103618301
96.51 0.01 98.36 0.00 93.94 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 98.66 0.10 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_stress_all.4195530031
96.52 0.01 98.36 0.00 93.94 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 98.76 0.10 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_stress_all.4001548415
96.54 0.01 98.36 0.00 93.94 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 98.86 0.10 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_and_tpm.1538379138
96.55 0.01 98.36 0.00 93.94 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 98.96 0.10 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_and_tpm_min_idle.556520805
96.57 0.01 98.36 0.00 93.94 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 99.06 0.10 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_mode.881974681
96.57 0.01 98.36 0.00 93.94 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 99.11 0.05 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_pass_addr_payload_swap.1173274018
96.58 0.01 98.36 0.00 93.94 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 99.16 0.05 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_mode.2115897492
96.59 0.01 98.36 0.00 93.94 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 99.21 0.05 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_and_tpm.3817410789
96.59 0.01 98.38 0.02 93.97 0.02 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 99.21 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_csb_read.3956325807
96.60 0.01 98.38 0.00 93.99 0.02 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 99.21 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.1510398409

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.2772422462
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.730232069
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2755981563
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.2514170508
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.3502705536
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.1947228115
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.3217577246
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2380514113
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.2871424373
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.1201070156
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2175423214
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3909212168
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.572960377
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.3011041343
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.86565661
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.2094230667
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.3057648209
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1797014283
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.2164461158
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.737476113
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_rw.15895221
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_intr_test.3128546211
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2172342838
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/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_read_hw_reg.2669022949
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/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_mode.291320396
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_mode_ignore_cmds.3808050695
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_intercept.62628397
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_mailbox.2897615667
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.3156345678
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_pass_cmd_filtering.3504056248
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/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_csb_read.3818611492
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_all.2404890123
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_and_tpm.1904097495
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_and_tpm_min_idle.2048319601
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_mode.3447394138
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.2672752526
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_intercept.2236314099
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/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_mode.1645812186
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_mode_ignore_cmds.2691733737
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_intercept.3895780228
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_mailbox.2151961643
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.50318306
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.169929886
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.528863055
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_stress_all.3980315326
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_all.68702523
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.3218033662
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_rw.3789929223
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.2106996480
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_upload.3512563240



Total test records in report: 1131
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_sts_read.4132440096 Aug 25 10:42:32 AM UTC 24 Aug 25 10:42:34 AM UTC 24 128267961 ps
T2 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_csb_read.3956325807 Aug 25 10:41:36 AM UTC 24 Aug 25 10:41:38 AM UTC 24 52318371 ps
T3 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_ram_cfg.192515123 Aug 25 10:41:38 AM UTC 24 Aug 25 10:41:40 AM UTC 24 26979431 ps
T4 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_sts_read.2689021675 Aug 25 10:41:39 AM UTC 24 Aug 25 10:41:41 AM UTC 24 756851763 ps
T5 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_rw.2418515073 Aug 25 10:41:39 AM UTC 24 Aug 25 10:41:42 AM UTC 24 165626321 ps
T6 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_pass_addr_payload_swap.651807047 Aug 25 10:41:40 AM UTC 24 Aug 25 10:41:49 AM UTC 24 301072607 ps
T7 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_mode.572772625 Aug 25 10:41:44 AM UTC 24 Aug 25 10:41:50 AM UTC 24 332245037 ps
T8 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_intercept.1260919688 Aug 25 10:41:43 AM UTC 24 Aug 25 10:41:50 AM UTC 24 340072726 ps
T9 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_stress_all.1756428015 Aug 25 10:41:50 AM UTC 24 Aug 25 10:41:52 AM UTC 24 61842359 ps
T10 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_sec_cm.2085254745 Aug 25 10:41:50 AM UTC 24 Aug 25 10:41:53 AM UTC 24 60164329 ps
T11 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_all.1538309341 Aug 25 10:41:38 AM UTC 24 Aug 25 10:41:54 AM UTC 24 924727619 ps
T36 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_alert_test.1901438036 Aug 25 10:41:52 AM UTC 24 Aug 25 10:41:55 AM UTC 24 136470309 ps
T12 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_csb_read.2617022515 Aug 25 10:41:52 AM UTC 24 Aug 25 10:41:55 AM UTC 24 20602094 ps
T13 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_and_tpm.136986722 Aug 25 10:41:50 AM UTC 24 Aug 25 10:42:27 AM UTC 24 1666351680 ps
T14 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_sts_read.3868396747 Aug 25 10:41:52 AM UTC 24 Aug 25 10:41:55 AM UTC 24 92608997 ps
T37 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_upload.1226496135 Aug 25 10:41:55 AM UTC 24 Aug 25 10:42:00 AM UTC 24 554048988 ps
T15 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_rw.3088063188 Aug 25 10:41:54 AM UTC 24 Aug 25 10:42:00 AM UTC 24 92888450 ps
T16 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_cfg_cmd.2394037765 Aug 25 10:41:44 AM UTC 24 Aug 25 10:42:00 AM UTC 24 752228911 ps
T17 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_upload.1633536045 Aug 25 10:42:34 AM UTC 24 Aug 25 10:42:41 AM UTC 24 207349380 ps
T92 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_alert_test.2845150751 Aug 25 10:42:00 AM UTC 24 Aug 25 10:42:03 AM UTC 24 36404647 ps
T18 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_csb_read.2281783794 Aug 25 10:42:01 AM UTC 24 Aug 25 10:42:03 AM UTC 24 15690400 ps
T19 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_mode.2520518666 Aug 25 10:41:56 AM UTC 24 Aug 25 10:42:03 AM UTC 24 702959881 ps
T20 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_stress_all.3887038699 Aug 25 10:42:00 AM UTC 24 Aug 25 10:42:03 AM UTC 24 237490691 ps
T25 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_read_hw_reg.1194467799 Aug 25 10:41:52 AM UTC 24 Aug 25 10:42:03 AM UTC 24 2584930605 ps
T28 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_sec_cm.1489765467 Aug 25 10:42:00 AM UTC 24 Aug 25 10:42:04 AM UTC 24 643839221 ps
T21 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_pass_cmd_filtering.3117347291 Aug 25 10:41:39 AM UTC 24 Aug 25 10:42:04 AM UTC 24 10388372526 ps
T26 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_sts_read.1040262560 Aug 25 10:42:03 AM UTC 24 Aug 25 10:42:05 AM UTC 24 79108383 ps
T22 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_read_buffer_direct.1539245871 Aug 25 10:41:58 AM UTC 24 Aug 25 10:42:05 AM UTC 24 275578732 ps
T27 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_read_hw_reg.3879467636 Aug 25 10:41:38 AM UTC 24 Aug 25 10:42:05 AM UTC 24 3834420589 ps
T38 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_rw.305107261 Aug 25 10:42:03 AM UTC 24 Aug 25 10:42:07 AM UTC 24 155411637 ps
T106 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_read_hw_reg.4064027047 Aug 25 10:42:02 AM UTC 24 Aug 25 10:42:08 AM UTC 24 806778481 ps
T23 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_pass_cmd_filtering.1948140978 Aug 25 10:42:05 AM UTC 24 Aug 25 10:42:10 AM UTC 24 150719832 ps
T24 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_read_buffer_direct.3126609265 Aug 25 10:41:47 AM UTC 24 Aug 25 10:42:10 AM UTC 24 1625053814 ps
T119 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_pass_addr_payload_swap.3577435239 Aug 25 10:42:05 AM UTC 24 Aug 25 10:42:10 AM UTC 24 239524948 ps
T29 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_sec_cm.3108931081 Aug 25 10:42:07 AM UTC 24 Aug 25 10:42:10 AM UTC 24 81837387 ps
T93 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_alert_test.4093780491 Aug 25 10:42:09 AM UTC 24 Aug 25 10:42:11 AM UTC 24 40919894 ps
T164 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_csb_read.250067269 Aug 25 10:42:09 AM UTC 24 Aug 25 10:42:11 AM UTC 24 74658831 ps
T112 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_mailbox.3534391458 Aug 25 10:41:43 AM UTC 24 Aug 25 10:42:12 AM UTC 24 2125805987 ps
T42 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_upload.2770788258 Aug 25 10:41:44 AM UTC 24 Aug 25 10:42:12 AM UTC 24 21016328990 ps
T70 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_intercept.3649963241 Aug 25 10:41:54 AM UTC 24 Aug 25 10:42:14 AM UTC 24 1114530345 ps
T45 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_all.4129878499 Aug 25 10:41:52 AM UTC 24 Aug 25 10:42:39 AM UTC 24 5237479581 ps
T71 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_sts_read.3957651195 Aug 25 10:42:12 AM UTC 24 Aug 25 10:42:15 AM UTC 24 430098701 ps
T72 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_upload.3582344406 Aug 25 10:42:05 AM UTC 24 Aug 25 10:42:15 AM UTC 24 3130398407 ps
T50 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_intercept.1293787433 Aug 25 10:42:05 AM UTC 24 Aug 25 10:42:15 AM UTC 24 368784917 ps
T73 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_cfg_cmd.650749050 Aug 25 10:42:06 AM UTC 24 Aug 25 10:42:16 AM UTC 24 1937941309 ps
T55 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_pass_cmd_filtering.530799807 Aug 25 10:41:54 AM UTC 24 Aug 25 10:42:16 AM UTC 24 11997037869 ps
T46 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_rw.4246225778 Aug 25 10:42:12 AM UTC 24 Aug 25 10:42:16 AM UTC 24 143646805 ps
T47 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_read_buffer_direct.1057887125 Aug 25 10:42:06 AM UTC 24 Aug 25 10:42:16 AM UTC 24 717520474 ps
T157 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_mode.3201989952 Aug 25 10:42:06 AM UTC 24 Aug 25 10:42:16 AM UTC 24 897178773 ps
T410 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_and_tpm.2779929497 Aug 25 10:42:16 AM UTC 24 Aug 25 10:42:18 AM UTC 24 122957666 ps
T104 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_cfg_cmd.2740667906 Aug 25 10:41:55 AM UTC 24 Aug 25 10:42:19 AM UTC 24 3409387789 ps
T411 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_alert_test.131014699 Aug 25 10:42:17 AM UTC 24 Aug 25 10:42:20 AM UTC 24 15542533 ps
T97 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_stress_all.2144586834 Aug 25 10:42:17 AM UTC 24 Aug 25 10:42:20 AM UTC 24 59692799 ps
T30 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_sec_cm.2721602577 Aug 25 10:42:17 AM UTC 24 Aug 25 10:42:20 AM UTC 24 116065322 ps
T91 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_cfg_cmd.2490951538 Aug 25 10:42:15 AM UTC 24 Aug 25 10:42:21 AM UTC 24 2455353288 ps
T85 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_mailbox.764242307 Aug 25 10:41:54 AM UTC 24 Aug 25 10:42:21 AM UTC 24 549231916 ps
T88 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_read_buffer_direct.400710189 Aug 25 10:42:16 AM UTC 24 Aug 25 10:42:22 AM UTC 24 428003111 ps
T43 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_all.3924908221 Aug 25 10:41:48 AM UTC 24 Aug 25 10:42:22 AM UTC 24 2348482780 ps
T412 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_all.2076851758 Aug 25 10:42:22 AM UTC 24 Aug 25 10:42:24 AM UTC 24 102537935 ps
T413 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_csb_read.2892805490 Aug 25 10:42:22 AM UTC 24 Aug 25 10:42:24 AM UTC 24 15476193 ps
T414 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_read_hw_reg.378405971 Aug 25 10:42:22 AM UTC 24 Aug 25 10:42:24 AM UTC 24 27682759 ps
T90 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_cfg_cmd.179399869 Aug 25 10:42:37 AM UTC 24 Aug 25 10:42:41 AM UTC 24 501755599 ps
T415 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_sts_read.881292078 Aug 25 10:42:22 AM UTC 24 Aug 25 10:42:24 AM UTC 24 100286184 ps
T113 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_upload.1940245956 Aug 25 10:42:14 AM UTC 24 Aug 25 10:42:25 AM UTC 24 2123933681 ps
T44 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_rw.2278596219 Aug 25 10:42:22 AM UTC 24 Aug 25 10:42:25 AM UTC 24 57022798 ps
T53 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_pass_addr_payload_swap.917438488 Aug 25 10:42:13 AM UTC 24 Aug 25 10:42:25 AM UTC 24 743888059 ps
T193 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_pass_cmd_filtering.1232931404 Aug 25 10:42:22 AM UTC 24 Aug 25 10:42:26 AM UTC 24 79856615 ps
T68 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_all.3680022049 Aug 25 10:42:03 AM UTC 24 Aug 25 10:42:26 AM UTC 24 1248465582 ps
T57 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_pass_addr_payload_swap.3285657102 Aug 25 10:42:22 AM UTC 24 Aug 25 10:42:28 AM UTC 24 498286669 ps
T56 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_mailbox.3341467871 Aug 25 10:42:05 AM UTC 24 Aug 25 10:42:28 AM UTC 24 1455765764 ps
T416 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_intercept.2266178689 Aug 25 10:42:24 AM UTC 24 Aug 25 10:42:29 AM UTC 24 426136354 ps
T114 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_pass_addr_payload_swap.4229598700 Aug 25 10:41:54 AM UTC 24 Aug 25 10:42:29 AM UTC 24 14899295885 ps
T417 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_alert_test.3724998064 Aug 25 10:42:27 AM UTC 24 Aug 25 10:42:29 AM UTC 24 13582838 ps
T31 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_sec_cm.248137100 Aug 25 10:42:27 AM UTC 24 Aug 25 10:42:30 AM UTC 24 42171445 ps
T183 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_mode.1240163038 Aug 25 10:42:37 AM UTC 24 Aug 25 10:42:42 AM UTC 24 193885258 ps
T418 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_csb_read.2326110656 Aug 25 10:42:29 AM UTC 24 Aug 25 10:42:31 AM UTC 24 114293722 ps
T188 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_mailbox.3092726747 Aug 25 10:42:14 AM UTC 24 Aug 25 10:42:32 AM UTC 24 1776979137 ps
T54 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_pass_cmd_filtering.1329245368 Aug 25 10:42:12 AM UTC 24 Aug 25 10:42:33 AM UTC 24 7587989797 ps
T69 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_rw.2830524345 Aug 25 10:42:32 AM UTC 24 Aug 25 10:42:34 AM UTC 24 22597253 ps
T419 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_pass_addr_payload_swap.1600554732 Aug 25 10:42:34 AM UTC 24 Aug 25 10:42:38 AM UTC 24 30330569 ps
T158 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_read_buffer_direct.4020742601 Aug 25 10:42:27 AM UTC 24 Aug 25 10:42:40 AM UTC 24 2290610025 ps
T420 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_read_hw_reg.2669022949 Aug 25 10:42:29 AM UTC 24 Aug 25 10:42:43 AM UTC 24 5663353262 ps
T107 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_cfg_cmd.3697503072 Aug 25 10:42:25 AM UTC 24 Aug 25 10:42:44 AM UTC 24 1330650729 ps
T177 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_intercept.3405056565 Aug 25 10:42:34 AM UTC 24 Aug 25 10:42:44 AM UTC 24 3702707057 ps
T189 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_intercept.428383048 Aug 25 10:42:13 AM UTC 24 Aug 25 10:42:44 AM UTC 24 3260799339 ps
T182 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_upload.2952029658 Aug 25 10:42:25 AM UTC 24 Aug 25 10:42:45 AM UTC 24 2477612945 ps
T421 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_alert_test.3742487453 Aug 25 10:42:42 AM UTC 24 Aug 25 10:42:46 AM UTC 24 29488657 ps
T214 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_mailbox.1817511990 Aug 25 10:42:34 AM UTC 24 Aug 25 10:42:46 AM UTC 24 4937737308 ps
T422 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_mode.3607094129 Aug 25 10:42:15 AM UTC 24 Aug 25 10:42:46 AM UTC 24 4933808993 ps
T89 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_mode_ignore_cmds.1959481657 Aug 25 10:42:16 AM UTC 24 Aug 25 10:42:47 AM UTC 24 3323259752 ps
T423 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_csb_read.2377523438 Aug 25 10:42:44 AM UTC 24 Aug 25 10:42:47 AM UTC 24 60521941 ps
T159 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_read_buffer_direct.3750243394 Aug 25 10:42:39 AM UTC 24 Aug 25 10:42:48 AM UTC 24 2002174007 ps
T105 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_all.3052482652 Aug 25 10:42:32 AM UTC 24 Aug 25 10:42:49 AM UTC 24 2823178160 ps
T86 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_intercept.3895780228 Aug 25 10:43:31 AM UTC 24 Aug 25 10:43:52 AM UTC 24 1643939393 ps
T424 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_read_hw_reg.3209026421 Aug 25 10:42:47 AM UTC 24 Aug 25 10:42:49 AM UTC 24 168341605 ps
T425 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_sts_read.3136987826 Aug 25 10:42:47 AM UTC 24 Aug 25 10:42:50 AM UTC 24 52601693 ps
T426 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_read_hw_reg.1524460167 Aug 25 10:42:12 AM UTC 24 Aug 25 10:42:51 AM UTC 24 7134437818 ps
T396 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_rw.3937028949 Aug 25 10:42:47 AM UTC 24 Aug 25 10:42:51 AM UTC 24 102366539 ps
T427 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_pass_addr_payload_swap.1304720564 Aug 25 10:42:47 AM UTC 24 Aug 25 10:42:52 AM UTC 24 203210145 ps
T428 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_mailbox.4222307681 Aug 25 10:42:49 AM UTC 24 Aug 25 10:42:53 AM UTC 24 32331285 ps
T429 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_alert_test.364797585 Aug 25 10:42:52 AM UTC 24 Aug 25 10:42:54 AM UTC 24 12975037 ps
T51 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_and_tpm_min_idle.3009389950 Aug 25 10:42:00 AM UTC 24 Aug 25 10:42:54 AM UTC 24 5671030634 ps
T430 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_csb_read.2554629342 Aug 25 10:42:52 AM UTC 24 Aug 25 10:42:54 AM UTC 24 23243277 ps
T160 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_read_buffer_direct.1280511536 Aug 25 10:42:50 AM UTC 24 Aug 25 10:42:56 AM UTC 24 236856947 ps
T248 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_cfg_cmd.681174538 Aug 25 10:42:49 AM UTC 24 Aug 25 10:42:57 AM UTC 24 403705428 ps
T431 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_sts_read.429920966 Aug 25 10:42:55 AM UTC 24 Aug 25 10:42:57 AM UTC 24 85789118 ps
T432 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_csb_read.2622275735 Aug 25 10:43:47 AM UTC 24 Aug 25 10:43:49 AM UTC 24 58111678 ps
T408 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_rw.2655446641 Aug 25 10:42:55 AM UTC 24 Aug 25 10:42:58 AM UTC 24 107945612 ps
T224 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_upload.859986216 Aug 25 10:42:49 AM UTC 24 Aug 25 10:42:58 AM UTC 24 1303443522 ps
T58 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_pass_cmd_filtering.1925695621 Aug 25 10:42:47 AM UTC 24 Aug 25 10:43:00 AM UTC 24 1799115288 ps
T215 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_pass_cmd_filtering.3504056248 Aug 25 10:42:56 AM UTC 24 Aug 25 10:43:01 AM UTC 24 78791936 ps
T433 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.3156345678 Aug 25 10:42:57 AM UTC 24 Aug 25 10:43:01 AM UTC 24 98937659 ps
T434 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_upload.762722702 Aug 25 10:43:00 AM UTC 24 Aug 25 10:43:04 AM UTC 24 41519066 ps
T111 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_mailbox.1802134829 Aug 25 10:42:24 AM UTC 24 Aug 25 10:43:04 AM UTC 24 30787684267 ps
T404 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_all.3740528108 Aug 25 10:42:55 AM UTC 24 Aug 25 10:43:05 AM UTC 24 9716507637 ps
T192 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_cfg_cmd.1825365660 Aug 25 10:43:00 AM UTC 24 Aug 25 10:43:05 AM UTC 24 105564536 ps
T161 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_mode.3742632769 Aug 25 10:42:49 AM UTC 24 Aug 25 10:43:07 AM UTC 24 2224083414 ps
T87 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_intercept.2959462311 Aug 25 10:42:49 AM UTC 24 Aug 25 10:43:08 AM UTC 24 1270774905 ps
T260 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_intercept.62628397 Aug 25 10:42:57 AM UTC 24 Aug 25 10:43:08 AM UTC 24 3624731805 ps
T162 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_read_buffer_direct.640323285 Aug 25 10:43:01 AM UTC 24 Aug 25 10:43:09 AM UTC 24 1323648737 ps
T185 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_mode.3036413399 Aug 25 10:42:25 AM UTC 24 Aug 25 10:43:09 AM UTC 24 3973520012 ps
T435 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_alert_test.305492791 Aug 25 10:43:07 AM UTC 24 Aug 25 10:43:09 AM UTC 24 23688668 ps
T436 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_csb_read.3818611492 Aug 25 10:43:08 AM UTC 24 Aug 25 10:43:11 AM UTC 24 45925472 ps
T437 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_read_hw_reg.3476331969 Aug 25 10:42:54 AM UTC 24 Aug 25 10:43:12 AM UTC 24 12282980243 ps
T438 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_sts_read.967740467 Aug 25 10:43:10 AM UTC 24 Aug 25 10:43:13 AM UTC 24 150238347 ps
T406 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_rw.2629063372 Aug 25 10:43:10 AM UTC 24 Aug 25 10:43:13 AM UTC 24 70456813 ps
T439 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_pass_cmd_filtering.683476004 Aug 25 10:43:11 AM UTC 24 Aug 25 10:43:16 AM UTC 24 31820468 ps
T395 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_all.1575200738 Aug 25 10:42:12 AM UTC 24 Aug 25 10:43:16 AM UTC 24 16643511386 ps
T187 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_pass_cmd_filtering.2991767837 Aug 25 10:42:32 AM UTC 24 Aug 25 10:43:17 AM UTC 24 15485263702 ps
T191 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_mailbox.2897615667 Aug 25 10:42:58 AM UTC 24 Aug 25 10:43:18 AM UTC 24 2424489337 ps
T440 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_read_hw_reg.2310482262 Aug 25 10:43:09 AM UTC 24 Aug 25 10:43:19 AM UTC 24 2498559392 ps
T441 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.2672752526 Aug 25 10:43:18 AM UTC 24 Aug 25 10:43:20 AM UTC 24 17970058 ps
T52 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_mode_ignore_cmds.3075203393 Aug 25 10:42:27 AM UTC 24 Aug 25 10:43:21 AM UTC 24 11503923128 ps
T394 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_rw.1534806402 Aug 25 10:43:52 AM UTC 24 Aug 25 10:43:56 AM UTC 24 185690277 ps
T194 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_intercept.2236314099 Aug 25 10:43:13 AM UTC 24 Aug 25 10:43:22 AM UTC 24 639681006 ps
T48 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_mode_ignore_cmds.1346537868 Aug 25 10:42:37 AM UTC 24 Aug 25 10:43:24 AM UTC 24 7620959467 ps
T163 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_mode.3447394138 Aug 25 10:43:17 AM UTC 24 Aug 25 10:43:25 AM UTC 24 505904897 ps
T391 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_all.1500547208 Aug 25 10:43:10 AM UTC 24 Aug 25 10:43:26 AM UTC 24 7086033709 ps
T442 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_alert_test.123421878 Aug 25 10:43:24 AM UTC 24 Aug 25 10:43:27 AM UTC 24 153538610 ps
T255 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_mailbox.3603869963 Aug 25 10:43:13 AM UTC 24 Aug 25 10:43:28 AM UTC 24 669580504 ps
T190 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_mailbox.2151961643 Aug 25 10:43:33 AM UTC 24 Aug 25 10:43:53 AM UTC 24 602495507 ps
T443 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_csb_read.3858705511 Aug 25 10:43:26 AM UTC 24 Aug 25 10:43:29 AM UTC 24 33383085 ps
T208 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_upload.2843750765 Aug 25 10:43:14 AM UTC 24 Aug 25 10:43:29 AM UTC 24 1959610703 ps
T444 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_read_buffer_direct.2462841984 Aug 25 10:43:19 AM UTC 24 Aug 25 10:43:30 AM UTC 24 1039579597 ps
T392 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_all.877323277 Aug 25 10:42:47 AM UTC 24 Aug 25 10:43:31 AM UTC 24 38428130564 ps
T445 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.2106996480 Aug 25 10:43:29 AM UTC 24 Aug 25 10:43:31 AM UTC 24 26328832 ps
T446 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_rw.3789929223 Aug 25 10:43:29 AM UTC 24 Aug 25 10:43:35 AM UTC 24 59792494 ps
T372 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_mode.291320396 Aug 25 10:43:00 AM UTC 24 Aug 25 10:43:37 AM UTC 24 5908305260 ps
T447 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.3218033662 Aug 25 10:43:27 AM UTC 24 Aug 25 10:43:37 AM UTC 24 988554335 ps
T256 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_cfg_cmd.1095340202 Aug 25 10:43:17 AM UTC 24 Aug 25 10:43:38 AM UTC 24 2107426933 ps
T60 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_and_tpm_min_idle.2169651075 Aug 25 10:42:07 AM UTC 24 Aug 25 10:43:38 AM UTC 24 4219284713 ps
T206 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.169929886 Aug 25 10:43:29 AM UTC 24 Aug 25 10:43:40 AM UTC 24 3497142149 ps
T203 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_cfg_cmd.28827696 Aug 25 10:43:35 AM UTC 24 Aug 25 10:43:41 AM UTC 24 731347407 ps
T59 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_all.166422023 Aug 25 10:42:07 AM UTC 24 Aug 25 10:43:44 AM UTC 24 10132667939 ps
T81 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_mode_ignore_cmds.419279221 Aug 25 10:41:56 AM UTC 24 Aug 25 10:43:46 AM UTC 24 21890152916 ps
T448 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_alert_test.2264750298 Aug 25 10:43:46 AM UTC 24 Aug 25 10:43:48 AM UTC 24 118902660 ps
T82 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_mode_ignore_cmds.974579603 Aug 25 10:42:06 AM UTC 24 Aug 25 10:43:49 AM UTC 24 8873468138 ps
T449 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_sts_read.3709434985 Aug 25 10:43:52 AM UTC 24 Aug 25 10:43:54 AM UTC 24 317954086 ps
T62 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_pass_addr_payload_swap.4040306424 Aug 25 10:43:12 AM UTC 24 Aug 25 10:43:56 AM UTC 24 32052463608 ps
T380 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_all.68702523 Aug 25 10:43:28 AM UTC 24 Aug 25 10:43:58 AM UTC 24 1862778086 ps
T196 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_pass_cmd_filtering.1702136423 Aug 25 10:43:54 AM UTC 24 Aug 25 10:44:00 AM UTC 24 418501603 ps
T450 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.528863055 Aug 25 10:43:38 AM UTC 24 Aug 25 10:44:01 AM UTC 24 2274073262 ps
T451 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_upload.3874561821 Aug 25 10:43:58 AM UTC 24 Aug 25 10:44:02 AM UTC 24 71532679 ps
T63 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.50318306 Aug 25 10:43:29 AM UTC 24 Aug 25 10:44:06 AM UTC 24 9238194939 ps
T110 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_intercept.865596060 Aug 25 10:43:58 AM UTC 24 Aug 25 10:44:07 AM UTC 24 213312442 ps
T452 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_read_hw_reg.2834173104 Aug 25 10:43:50 AM UTC 24 Aug 25 10:44:07 AM UTC 24 18221971465 ps
T64 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_all.2807349110 Aug 25 10:43:02 AM UTC 24 Aug 25 10:44:08 AM UTC 24 2207854198 ps
T65 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_pass_addr_payload_swap.900518073 Aug 25 10:43:55 AM UTC 24 Aug 25 10:44:09 AM UTC 24 315809909 ps
T453 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_alert_test.4158667134 Aug 25 10:44:08 AM UTC 24 Aug 25 10:44:11 AM UTC 24 11297933 ps
T186 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_and_tpm.3150969897 Aug 25 10:44:03 AM UTC 24 Aug 25 10:44:11 AM UTC 24 154055372 ps
T83 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_upload.3512563240 Aug 25 10:43:33 AM UTC 24 Aug 25 10:44:11 AM UTC 24 10676538922 ps
T373 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_mode.1645812186 Aug 25 10:43:36 AM UTC 24 Aug 25 10:44:12 AM UTC 24 1522764620 ps
T454 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_csb_read.3300086172 Aug 25 10:44:09 AM UTC 24 Aug 25 10:44:12 AM UTC 24 34781324 ps
T455 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_read_buffer_direct.1794254399 Aug 25 10:44:01 AM UTC 24 Aug 25 10:44:12 AM UTC 24 404938157 ps
T456 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_sts_read.308584350 Aug 25 10:44:12 AM UTC 24 Aug 25 10:44:14 AM UTC 24 129243929 ps
T457 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_rw.963600337 Aug 25 10:44:13 AM UTC 24 Aug 25 10:44:15 AM UTC 24 14883655 ps
T385 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_all.1165698728 Aug 25 10:43:50 AM UTC 24 Aug 25 10:44:16 AM UTC 24 3829492554 ps
T458 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_cfg_cmd.1964808660 Aug 25 10:43:59 AM UTC 24 Aug 25 10:44:16 AM UTC 24 2065415006 ps
T108 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_mailbox.1554562248 Aug 25 10:43:58 AM UTC 24 Aug 25 10:45:13 AM UTC 24 4592295792 ps
T84 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_and_tpm.1904097495 Aug 25 10:43:21 AM UTC 24 Aug 25 10:44:19 AM UTC 24 6111432908 ps
T459 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_read_hw_reg.3912742384 Aug 25 10:44:12 AM UTC 24 Aug 25 10:44:20 AM UTC 24 1310902153 ps
T460 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_pass_cmd_filtering.1846144408 Aug 25 10:44:13 AM UTC 24 Aug 25 10:44:20 AM UTC 24 337054823 ps
T225 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_intercept.3575369539 Aug 25 10:44:14 AM UTC 24 Aug 25 10:44:21 AM UTC 24 387237821 ps
T242 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_mailbox.1109375306 Aug 25 10:44:15 AM UTC 24 Aug 25 10:44:22 AM UTC 24 324774905 ps
T32 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_stress_all.946594627 Aug 25 10:42:27 AM UTC 24 Aug 25 10:44:23 AM UTC 24 11298323993 ps
T98 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_and_tpm.1761053166 Aug 25 10:42:07 AM UTC 24 Aug 25 10:44:23 AM UTC 24 28702422634 ps
T201 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_pass_addr_payload_swap.219210324 Aug 25 10:44:13 AM UTC 24 Aug 25 10:44:23 AM UTC 24 396483407 ps
T229 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_cfg_cmd.2450651302 Aug 25 10:44:17 AM UTC 24 Aug 25 10:44:25 AM UTC 24 336969392 ps
T184 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_mode_ignore_cmds.1647051679 Aug 25 10:44:01 AM UTC 24 Aug 25 10:44:25 AM UTC 24 6555649637 ps
T461 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_alert_test.3093671260 Aug 25 10:44:24 AM UTC 24 Aug 25 10:44:26 AM UTC 24 15464654 ps
T462 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_csb_read.4041194968 Aug 25 10:44:24 AM UTC 24 Aug 25 10:44:26 AM UTC 24 30002908 ps
T249 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_intercept.3380490907 Aug 25 10:44:49 AM UTC 24 Aug 25 10:45:15 AM UTC 24 2260184506 ps
T463 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_all.3608058432 Aug 25 10:44:26 AM UTC 24 Aug 25 10:44:29 AM UTC 24 34568192 ps
T179 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_upload.1895817863 Aug 25 10:44:16 AM UTC 24 Aug 25 10:44:29 AM UTC 24 2672711350 ps
T464 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_sts_read.4219521578 Aug 25 10:44:27 AM UTC 24 Aug 25 10:44:30 AM UTC 24 149439595 ps
T465 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_mode.2642814684 Aug 25 10:44:17 AM UTC 24 Aug 25 10:44:31 AM UTC 24 1633996481 ps
T400 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_rw.1423984576 Aug 25 10:44:28 AM UTC 24 Aug 25 10:44:32 AM UTC 24 42218208 ps
T33 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_stress_all.2213288240 Aug 25 10:42:42 AM UTC 24 Aug 25 10:44:33 AM UTC 24 13401779887 ps
T381 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_all.3380718839 Aug 25 10:44:12 AM UTC 24 Aug 25 10:44:35 AM UTC 24 20554707560 ps
T49 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_and_tpm.234415553 Aug 25 10:42:42 AM UTC 24 Aug 25 10:44:37 AM UTC 24 13781015472 ps
T207 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_upload.2235208692 Aug 25 10:44:32 AM UTC 24 Aug 25 10:44:38 AM UTC 24 251905027 ps
T250 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_cfg_cmd.1931333340 Aug 25 10:44:32 AM UTC 24 Aug 25 10:44:38 AM UTC 24 320357109 ps
T343 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_and_tpm_min_idle.2048319601 Aug 25 10:43:22 AM UTC 24 Aug 25 10:44:41 AM UTC 24 2387482127 ps
T466 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_read_buffer_direct.1304057405 Aug 25 10:44:21 AM UTC 24 Aug 25 10:44:43 AM UTC 24 18340411288 ps
T359 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_mode.1140811254 Aug 25 10:44:33 AM UTC 24 Aug 25 10:44:43 AM UTC 24 412985502 ps
T34 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_stress_all.120221836 Aug 25 10:44:41 AM UTC 24 Aug 25 10:44:44 AM UTC 24 197848351 ps
T202 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_mailbox.732331766 Aug 25 10:44:31 AM UTC 24 Aug 25 10:44:45 AM UTC 24 374665633 ps
T467 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_alert_test.1689073158 Aug 25 10:44:43 AM UTC 24 Aug 25 10:44:45 AM UTC 24 12013480 ps
T247 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_pass_addr_payload_swap.3958335471 Aug 25 10:44:29 AM UTC 24 Aug 25 10:44:46 AM UTC 24 2840029479 ps
T468 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_csb_read.441613276 Aug 25 10:44:46 AM UTC 24 Aug 25 10:44:48 AM UTC 24 56658957 ps
T197 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_intercept.23543333 Aug 25 10:45:10 AM UTC 24 Aug 25 10:45:15 AM UTC 24 92148852 ps
T469 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_sts_read.2576958229 Aug 25 10:44:46 AM UTC 24 Aug 25 10:44:48 AM UTC 24 169876533 ps
T403 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_rw.4115925073 Aug 25 10:44:46 AM UTC 24 Aug 25 10:44:49 AM UTC 24 60664887 ps
T470 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_mode.1362856766 Aug 25 10:43:59 AM UTC 24 Aug 25 10:44:50 AM UTC 24 2337164463 ps
T471 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_read_buffer_direct.280562203 Aug 25 10:44:36 AM UTC 24 Aug 25 10:44:51 AM UTC 24 766351814 ps
T472 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_read_hw_reg.293311888 Aug 25 10:44:26 AM UTC 24 Aug 25 10:44:53 AM UTC 24 14782684329 ps
T259 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_intercept.602925947 Aug 25 10:44:30 AM UTC 24 Aug 25 10:44:53 AM UTC 24 7887081399 ps
T198 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_mailbox.4057216164 Aug 25 10:44:49 AM UTC 24 Aug 25 10:44:58 AM UTC 24 368076536 ps
T362 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_pass_cmd_filtering.1482186150 Aug 25 10:44:29 AM UTC 24 Aug 25 10:45:01 AM UTC 24 8717173440 ps
T342 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_and_tpm.170859668 Aug 25 10:44:22 AM UTC 24 Aug 25 10:45:02 AM UTC 24 2728972158 ps
T473 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_read_buffer_direct.706001303 Aug 25 10:44:55 AM UTC 24 Aug 25 10:45:03 AM UTC 24 2655866864 ps
T257 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_pass_addr_payload_swap.623276207 Aug 25 10:44:49 AM UTC 24 Aug 25 10:45:03 AM UTC 24 1906741044 ps
T204 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_cfg_cmd.3124275420 Aug 25 10:44:50 AM UTC 24 Aug 25 10:45:03 AM UTC 24 1135748780 ps
T66 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_and_tpm.1459788156 Aug 25 10:42:27 AM UTC 24 Aug 25 10:45:05 AM UTC 24 15372033330 ps
T39 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_and_tpm_min_idle.1910476688 Aug 25 10:42:27 AM UTC 24 Aug 25 10:45:05 AM UTC 24 36439130016 ps
T35 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_stress_all.3980315326 Aug 25 10:43:42 AM UTC 24 Aug 25 10:45:05 AM UTC 24 4134832403 ps
T474 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_alert_test.477882767 Aug 25 10:45:04 AM UTC 24 Aug 25 10:45:06 AM UTC 24 11921423 ps
T475 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_csb_read.4061880033 Aug 25 10:45:04 AM UTC 24 Aug 25 10:45:07 AM UTC 24 18269383 ps
T476 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_read_hw_reg.3309088912 Aug 25 10:44:46 AM UTC 24 Aug 25 10:45:08 AM UTC 24 3427563263 ps
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T477 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_sts_read.1807846147 Aug 25 10:45:06 AM UTC 24 Aug 25 10:45:09 AM UTC 24 114425723 ps
T233 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_pass_cmd_filtering.2542871837 Aug 25 10:44:47 AM UTC 24 Aug 25 10:45:13 AM UTC 24 16270737788 ps
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T478 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_pass_addr_payload_swap.1501182381 Aug 25 10:45:09 AM UTC 24 Aug 25 10:45:13 AM UTC 24 123059673 ps
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T405 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_rw.611990255 Aug 25 10:45:07 AM UTC 24 Aug 25 10:45:20 AM UTC 24 976187885 ps
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T480 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_csb_read.2059672125 Aug 25 10:45:24 AM UTC 24 Aug 25 10:45:26 AM UTC 24 25390811 ps
T175 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_stress_all.1483561464 Aug 25 10:42:52 AM UTC 24 Aug 25 10:45:27 AM UTC 24 8338572247 ps
T481 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_sts_read.653915969 Aug 25 10:45:28 AM UTC 24 Aug 25 10:45:30 AM UTC 24 37109165 ps
T482 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_read_hw_reg.2426683438 Aug 25 10:45:06 AM UTC 24 Aug 25 10:45:34 AM UTC 24 14550928012 ps
T483 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_read_hw_reg.2513007449 Aug 25 10:45:27 AM UTC 24 Aug 25 10:45:34 AM UTC 24 1057931002 ps
T484 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_read_buffer_direct.725572113 Aug 25 10:45:16 AM UTC 24 Aug 25 10:45:35 AM UTC 24 973214702 ps
T67 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_all.290926702 Aug 25 10:44:59 AM UTC 24 Aug 25 10:45:36 AM UTC 24 1943940959 ps
T244 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_upload.4251464835 Aug 25 10:44:50 AM UTC 24 Aug 25 10:45:37 AM UTC 24 34834623709 ps
T407 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_rw.546210572 Aug 25 10:45:31 AM UTC 24 Aug 25 10:45:37 AM UTC 24 579241459 ps
T99 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_all.4214921391 Aug 25 10:42:16 AM UTC 24 Aug 25 10:45:39 AM UTC 24 43005611304 ps
T211 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_upload.49657081 Aug 25 10:45:37 AM UTC 24 Aug 25 10:45:43 AM UTC 24 168192788 ps
T178 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_and_tpm_min_idle.28348594 Aug 25 10:44:23 AM UTC 24 Aug 25 10:45:43 AM UTC 24 66024923552 ps
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