Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	35651	1			T6	10		T16	10		T17	4
auto[SpiFlashAddrCfg]	7499	1			T6	4		T17	4		T21	4
auto[SpiFlashAddr3b]	9070	1			T6	2		T7	1		T8	2
auto[SpiFlashAddr4b]	7211	1			T6	8		T8	4		T17	2

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33786

1

T7

1

T8

6

T16

10

auto[1]

25645

1

T6

24

T43

36

T53

22

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31361

1

T6

12

T8

6

T16

10

auto[1]

28070

1

T6

12

T7

1

T17

4

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	40213	1			T6	12		T8	2		T16	10
values[1]	1147	1			T43	3		T54	2		T177	6
values[2]	1351	1			T21	4		T50	2		T43	5
values[3]	1456	1			T6	2		T21	2		T50	2
values[4]	1394	1			T21	2		T43	3		T89	2
values[5]	1413	1			T70	2		T43	6		T56	10
values[6]	1410	1			T6	4		T8	4		T50	2
values[7]	1422	1			T6	2		T17	2		T43	4
values[8]	9625	1			T6	4		T7	1		T17	4

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32524

1

T6

24

T8

6

T16

10

auto[1]

26907

1

T7

1

T19

2

T157

1

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

56237

1

T6

20

T7

1

T8

6

write

3194

1

T6

4

T42

4

T43

11

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

18796

1

T6

8

T7

1

T8

4

valids[0x1]

40635

1

T6

16

T8

2

T17

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1653	1			T70	2		T43	6		T113	4
internal_process_ops[0x5a]	1561	1			T6	2		T8	2		T21	4
internal_process_ops[0x05]	21770	1			T6	6		T17	2		T112	4
internal_process_ops[0x35]	1578	1			T42	2		T70	2		T72	2
internal_process_ops[0x15]	1538	1			T6	2		T55	6		T43	3
internal_process_ops[0x03]	1099	1			T23	2		T50	2		T114	4
internal_process_ops[0x0b]	1008	1			T42	2		T50	2		T55	2
internal_process_ops[0x3b]	1037	1			T6	4		T70	2		T55	2
internal_process_ops[0x6b]	1077	1			T17	2		T21	2		T70	4
internal_process_ops[0xbb]	1025	1			T7	1		T8	4		T19	2
internal_process_ops[0xeb]	970	1			T50	6		T43	1		T56	4

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

57887

1

T6

20

T7

1

T8

6

auto[1]

1544

1

T6

4

T43

4

T53

2

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

57115

1

T6

24

T7

1

T8

6

auto[1]

2316

1

T42

4

T43

5

T52

9

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10880

1

T16

10

T17

4

T21

6

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7096

1

T6

10

T53

2

T57

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2186

1

T17

4

T21

4

T23

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1809

1

T53

2

T114

2

T60

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2627

1

T8

2

T21

6

T70

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2333

1

T6

2

T53

10

T114

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2066

1

T8

4

T17

2

T70

4

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1830

1

T6

8

T53

6

T57

6

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

121

1

T35

2

T99

1

T178

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

109

1

T60

1

T59

2

T64

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

89

1

T59

2

T64

3

T35

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

86

1

T60

1

T59

1

T65

4

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

129

1

T42

4

T58

2

T179

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

91

1

T99

1

T61

1

T180

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

102

1

T59

2

T66

3

T181

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

121

1

T6

4

T59

2

T62

4

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

107

1

T182

2

T59

1

T64

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

89

1

T59

1

T33

1

T99

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

114

1

T60

3

T59

4

T33

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

114

1

T53

2

T63

2

T64

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

132

1

T54

2

T64

2

T66

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

112

1

T64

2

T35

4

T67

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

90

1

T59

1

T66

1

T61

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

91

1

T66

2

T35

2

T61

3

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9982

1

T43

172

T89

22

T51

18

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6885

1

T43

12

T89

10

T51

4

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1430

1

T157

1

T43

11

T89

8

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1279

1

T43

5

T89

1

T51

5

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1685

1

T7

1

T19

2

T43

9

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1610

1

T43

8

T89

2

T51

10

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1277

1

T43

7

T183

2

T89

5

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1262

1

T43

7

T89

8

T51

4

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

94

1

T51

2

T52

2

T48

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

101

1

T43

4

T81

1

T84

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

118

1

T81

5

T32

4

T98

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

90

1

T82

2

T32

5

T49

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

87

1

T52

2

T98

2

T184

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

86

1

T48

2

T81

1

T32

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

93

1

T43

3

T89

1

T52

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

86

1

T52

1

T48

1

T32

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

108

1

T43

3

T89

1

T48

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

93

1

T52

1

T81

2

T84

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

94

1

T43

1

T48

1

T84

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

96

1

T52

2

T48

1

T81

7

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

112

1

T89

1

T185

1

T81

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

82

1

T81

1

T186

1

T32

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

60

1

T52

1

T48

2

T81

4

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

97

1

T48

5

T82

2

T32

3

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	4105	1			T16	10		T17	2		T21	2
auto[0]	values[0]	valids[0x1]	16911	1			T6	12		T8	2		T17	2
auto[0]	values[1]	valids[0x1]	634	1			T54	2		T177	6		T59	4
auto[0]	values[2]	valids[0x0]	543	1			T53	2		T57	2		T177	2
auto[0]	values[2]	valids[0x1]	285	1			T21	4		T50	2		T59	1
auto[0]	values[3]	valids[0x0]	504	1			T50	2		T59	6		T64	2
auto[0]	values[3]	valids[0x1]	365	1			T6	2		T21	2		T55	2
auto[0]	values[4]	valids[0x0]	559	1			T21	2		T59	5		T62	2
auto[0]	values[4]	valids[0x1]	305	1			T59	2		T64	3		T33	3
auto[0]	values[5]	valids[0x0]	516	1			T70	2		T56	10		T187	2
auto[0]	values[5]	valids[0x1]	321	1			T114	4		T54	2		T182	4
auto[0]	values[6]	valids[0x0]	522	1			T6	4		T8	4		T50	2
auto[0]	values[6]	valids[0x1]	321	1			T55	2		T188	8		T59	6
auto[0]	values[7]	valids[0x0]	593	1			T17	2		T189	4		T60	4
auto[0]	values[7]	valids[0x1]	327	1			T6	2		T54	6		T190	2
auto[0]	values[8]	valids[0x0]	3553	1			T6	4		T17	4		T70	4
auto[0]	values[8]	valids[0x1]	2160	1			T23	2		T72	2		T53	2
auto[1]	values[0]	valids[0x0]	3595	1			T43	16		T89	13		T51	12
auto[1]	values[0]	valids[0x1]	15602	1			T43	180		T183	3		T89	23
auto[1]	values[1]	valids[0x1]	513	1			T43	3		T89	3		T51	1
auto[1]	values[2]	valids[0x0]	325	1			T43	2		T185	1		T52	2
auto[1]	values[2]	valids[0x1]	198	1			T43	3		T52	2		T48	1
auto[1]	values[3]	valids[0x0]	349	1			T43	4		T89	1		T51	2
auto[1]	values[3]	valids[0x1]	238	1			T161	1		T52	6		T48	3
auto[1]	values[4]	valids[0x0]	324	1			T43	2		T51	1		T52	3
auto[1]	values[4]	valids[0x1]	206	1			T43	1		T89	2		T52	1
auto[1]	values[5]	valids[0x0]	364	1			T43	3		T89	1		T51	7
auto[1]	values[5]	valids[0x1]	212	1			T43	3		T48	3		T81	2
auto[1]	values[6]	valids[0x0]	347	1			T43	2		T51	2		T52	1
auto[1]	values[6]	valids[0x1]	220	1			T43	1		T52	1		T48	1
auto[1]	values[7]	valids[0x0]	305	1			T43	4		T89	2		T51	1
auto[1]	values[7]	valids[0x1]	197	1			T52	1		T48	1		T81	1
auto[1]	values[8]	valids[0x0]	2292	1			T7	1		T19	2		T157	1
auto[1]	values[8]	valids[0x1]	1620	1			T43	11		T89	7		T51	11