Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3311027

1

T6

1

T7

58

T8

715

auto[1]

31996

1

T42

32

T43

142

T52

754

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

870398

1

T6

1

T7

58

T8

715

auto[1]

2472625

1

T17

256

T42

44

T72

1022

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	613814	1			T6	1		T7	55		T8	167
auto[524288:1048575]	328082	1			T8	164		T16	5		T70	135
auto[1048576:1572863]	384353	1			T8	176		T16	454		T112	628
auto[1572864:2097151]	409784	1			T8	207		T112	359		T70	1515
auto[2097152:2621439]	424946	1			T16	152		T112	258		T70	1697
auto[2621440:3145727]	419207	1			T16	1006		T19	296		T112	98
auto[3145728:3670015]	385713	1			T7	3		T112	291		T70	330
auto[3670016:4194303]	377124	1			T8	1		T16	653		T112	320

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2504967

1

T6

1

T7

3

T8

13

auto[1]

838056

1

T7

55

T8

702

T16

2836

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2928274

1

T6

1

T7

58

T8

715

auto[1]

414749

1

T16

257

T73

296

T90

10

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	192043	1			T6	1		T7	55		T8	167
auto[0]	auto[0]	auto[0:524287]	auto[1]	370262	1			T17	256		T42	16		T72	1022
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	74290	1			T8	164		T16	5		T70	135
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	208956	1			T43	512		T51	256		T52	506
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	81563	1			T8	176		T16	454		T112	628
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	244528	1			T89	4235		T260	257		T255	1368
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	100828	1			T8	207		T112	359		T70	1515
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	244483	1			T43	257		T260	4		T52	128
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	104343	1			T16	152		T112	258		T70	1697
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	258563	1			T43	6		T81	6074		T84	512
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	103562	1			T16	1006		T19	296		T112	98
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	264669	1			T43	1		T86	512		T52	3236
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	104184	1			T7	3		T112	291		T70	330
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	229377	1			T43	643		T89	2179		T51	896
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	97672	1			T8	1		T16	396		T112	320
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	221410	1			T43	257		T260	5		T52	1778
auto[0]	auto[1]	auto[0:524287]	auto[0]	698	1			T90	10		T89	8		T52	24
auto[0]	auto[1]	auto[0:524287]	auto[1]	46901	1			T52	4		T48	256		T49	650
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	970	1			T52	9		T48	3		T59	3
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	40016	1			T59	513		T98	2		T49	1154
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	810	1			T73	1		T52	14		T48	3
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	52623	1			T64	1		T98	256		T49	1181
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	1706	1			T52	7		T60	1		T59	8
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	57668	1			T59	3119		T64	1024		T32	512
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	1032	1			T73	293		T51	3		T248	2
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	57856	1			T51	256		T59	1		T82	512
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	628	1			T73	2		T52	5		T48	11
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	46866	1			T48	512		T60	1		T64	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	1702	1			T89	29		T81	8		T82	4
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	47090	1			T89	512		T51	3		T32	368
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	832	1			T16	257		T48	8		T203	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	52896	1			T48	2925		T98	25		T39	1
auto[1]	auto[0]	auto[0:524287]	auto[0]	429	1			T42	4		T52	12		T48	16
auto[1]	auto[0]	auto[0:524287]	auto[1]	2837	1			T42	28		T52	286		T60	3
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	288	1			T48	23		T59	1		T81	12
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2952	1			T48	594		T59	11		T81	72
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	368	1			T59	4		T82	7		T84	2
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	3964	1			T59	156		T84	4		T98	33
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	404	1			T43	1		T52	18		T48	5
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	4099	1			T43	51		T59	46		T64	86
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	332	1			T43	1		T48	11		T81	8
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2242	1			T43	48		T81	72		T98	29
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	371	1			T43	1		T52	10		T48	6
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2739	1			T43	17		T81	54		T84	15
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	340	1			T43	1		T48	7		T81	15
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2355	1			T43	2		T64	104		T32	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	343	1			T43	1		T52	5		T48	19
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	3478	1			T43	19		T52	418		T48	691
auto[1]	auto[1]	auto[0:524287]	auto[0]	100	1			T52	5		T48	3		T66	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	544	1			T66	2		T336	2		T212	82
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	92	1			T59	1		T98	2		T49	2
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	518	1			T98	12		T49	15		T178	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	56	1			T64	1		T49	3		T39	4
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	441	1			T64	53		T49	66		T39	20
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	76	1			T59	1		T39	1		T360	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	520	1			T59	4		T39	47		T360	27
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	100	1			T59	1		T35	1		T99	3
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	478	1			T59	14		T35	15		T99	58
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	75	1			T60	1		T64	1		T49	2
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	297	1			T60	6		T64	11		T49	4
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	84	1			T32	1		T33	2		T49	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	581	1			T33	10		T49	12		T342	25
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	77	1			T357	10		T223	1		T361	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	416	1			T223	1		T361	1		T142	74

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2067261	1			T6	1		T7	3		T8	13
auto[0]	auto[0]	auto[1]	833472	1			T7	55		T8	702		T16	2834
auto[0]	auto[1]	auto[0]	406374	1			T16	255		T73	4		T90	3
auto[0]	auto[1]	auto[1]	3920	1			T16	2		T73	292		T90	7
auto[1]	auto[0]	auto[0]	26995	1			T42	30		T43	141		T52	744
auto[1]	auto[0]	auto[1]	546	1			T42	2		T43	1		T52	5
auto[1]	auto[1]	auto[0]	4337	1			T52	4		T48	2		T60	7
auto[1]	auto[1]	auto[1]	118	1			T52	1		T48	1		T59	1