Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2557197	1			T1	1		T2	1		T3	1
all_pins[1]	2557197	1			T1	1		T2	1		T3	1
all_pins[2]	2557197	1			T1	1		T2	1		T3	1
all_pins[3]	2557197	1			T1	1		T2	1		T3	1
all_pins[4]	2557197	1			T1	1		T2	1		T3	1
all_pins[5]	2557197	1			T1	1		T2	1		T3	1
all_pins[6]	2557197	1			T1	1		T2	1		T3	1
all_pins[7]	2557197	1			T1	1		T2	1		T3	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	20380601	1			T1	8		T2	8		T3	8
values[0x1]	76975	1			T9	25		T20	16		T97	19
transitions[0x0=>0x1]	75702	1			T9	21		T20	13		T97	14
transitions[0x1=>0x0]	75718	1			T9	21		T20	13		T97	14

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2556714	1			T1	1		T2	1		T3	1
all_pins[0]	values[0x1]	483	1			T9	2		T97	2		T32	188
all_pins[0]	transitions[0x0=>0x1]	405	1			T9	2		T97	2		T32	188
all_pins[0]	transitions[0x1=>0x0]	341	1			T9	7		T20	1		T97	1
all_pins[1]	values[0x0]	2556778	1			T1	1		T2	1		T3	1
all_pins[1]	values[0x1]	419	1			T9	7		T20	1		T97	1
all_pins[1]	transitions[0x0=>0x1]	296	1			T9	6		T20	1		T97	1
all_pins[1]	transitions[0x1=>0x0]	211	1			T9	1		T20	3		T97	1
all_pins[2]	values[0x0]	2556863	1			T1	1		T2	1		T3	1
all_pins[2]	values[0x1]	334	1			T9	2		T20	3		T97	1
all_pins[2]	transitions[0x0=>0x1]	270	1			T9	1		T20	1		T97	1
all_pins[2]	transitions[0x1=>0x0]	172	1			T20	2		T97	3		T32	2
all_pins[3]	values[0x0]	2556961	1			T1	1		T2	1		T3	1
all_pins[3]	values[0x1]	236	1			T9	1		T20	4		T97	3
all_pins[3]	transitions[0x0=>0x1]	179	1			T9	1		T20	4		T97	2
all_pins[3]	transitions[0x1=>0x0]	165	1			T9	3		T20	2		T97	3
all_pins[4]	values[0x0]	2556975	1			T1	1		T2	1		T3	1
all_pins[4]	values[0x1]	222	1			T9	3		T20	2		T97	4
all_pins[4]	transitions[0x0=>0x1]	169	1			T9	2		T20	2		T97	2
all_pins[4]	transitions[0x1=>0x0]	1258	1			T9	1		T97	2		T33	360
all_pins[5]	values[0x0]	2555886	1			T1	1		T2	1		T3	1
all_pins[5]	values[0x1]	1311	1			T9	2		T97	4		T32	1
all_pins[5]	transitions[0x0=>0x1]	508	1			T9	1		T97	3		T32	1
all_pins[5]	transitions[0x1=>0x0]	72982	1			T9	5		T20	2		T97	1
all_pins[6]	values[0x0]	2483412	1			T1	1		T2	1		T3	1
all_pins[6]	values[0x1]	73785	1			T9	6		T20	2		T97	2
all_pins[6]	transitions[0x0=>0x1]	73731	1			T9	6		T20	1		T97	2
all_pins[6]	transitions[0x1=>0x0]	131	1			T9	2		T20	3		T97	2
all_pins[7]	values[0x0]	2557012	1			T1	1		T2	1		T3	1
all_pins[7]	values[0x1]	185	1			T9	2		T20	4		T97	2
all_pins[7]	transitions[0x0=>0x1]	144	1			T9	2		T20	4		T97	1
all_pins[7]	transitions[0x1=>0x0]	458	1			T9	2		T97	1		T32	187