Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18649

1

T8

6

T16

10

T17

10

auto[1]

13875

1

T6

24

T53

22

T57

8

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3764	1			T21	16		T50	14		T73	20
values[1]	3895	1			T8	6		T112	4		T86	6
values[2]	4209	1			T55	14		T113	10		T53	22
values[3]	4166	1			T85	8		T248	6		T194	12
values[4]	4388	1			T42	44		T70	10		T215	2
values[5]	4024	1			T17	10		T188	10		T58	14
values[6]	4535	1			T6	24		T114	18		T189	10
values[7]	3543	1			T16	10		T23	2		T72	6

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3876	1			T70	10		T53	22		T192	20
values[1]	4314	1			T8	6		T23	2		T90	2
values[2]	3737	1			T73	20		T55	14		T113	10
values[3]	4783	1			T6	24		T42	44		T85	8
values[4]	3534	1			T17	10		T72	6		T50	14
values[5]	4048	1			T16	10		T112	4		T57	8
values[6]	3775	1			T21	16		T60	31		T64	85
values[7]	4457	1			T91	14		T188	10		T111	14

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	205	1			T203	6		T66	48		T277	8
auto[0]	values[0]	values[1]	436	1			T90	2		T362	4		T209	16
auto[0]	values[0]	values[2]	434	1			T73	20		T107	12		T61	11
auto[0]	values[0]	values[3]	345	1			T54	22		T108	10		T61	9
auto[0]	values[0]	values[4]	200	1			T50	14		T212	9		T223	10
auto[0]	values[0]	values[5]	298	1			T177	14		T182	16		T169	17
auto[0]	values[0]	values[6]	209	1			T21	16		T181	15		T205	22
auto[0]	values[0]	values[7]	160	1			T253	20		T363	2		T364	38
auto[0]	values[1]	values[0]	417	1			T59	32		T181	17		T144	20
auto[0]	values[1]	values[1]	387	1			T8	6		T99	14		T200	10
auto[0]	values[1]	values[2]	350	1			T99	9		T61	9		T280	10
auto[0]	values[1]	values[3]	281	1			T64	79		T249	12		T33	9
auto[0]	values[1]	values[4]	261	1			T256	6		T99	9		T280	10
auto[0]	values[1]	values[5]	180	1			T112	4		T86	6		T223	9
auto[0]	values[1]	values[6]	142	1			T35	13		T61	13		T210	14
auto[0]	values[1]	values[7]	196	1			T142	13		T254	14		T218	12
auto[0]	values[2]	values[0]	436	1			T87	6		T210	25		T365	10
auto[0]	values[2]	values[1]	214	1			T193	2		T191	6		T66	11
auto[0]	values[2]	values[2]	199	1			T55	14		T113	10		T206	8
auto[0]	values[2]	values[3]	293	1			T56	20		T33	8		T66	17
auto[0]	values[2]	values[4]	266	1			T59	27		T212	34		T366	10
auto[0]	values[2]	values[5]	527	1			T99	10		T223	86		T213	12
auto[0]	values[2]	values[6]	295	1			T33	8		T267	12		T210	12
auto[0]	values[2]	values[7]	320	1			T35	27		T218	10		T263	24
auto[0]	values[3]	values[0]	281	1			T110	6		T181	14		T210	12
auto[0]	values[3]	values[1]	291	1			T255	6		T233	20		T210	10
auto[0]	values[3]	values[2]	159	1			T194	12		T226	12		T99	14
auto[0]	values[3]	values[3]	319	1			T85	8		T248	6		T99	11
auto[0]	values[3]	values[4]	373	1			T208	2		T196	2		T33	16
auto[0]	values[3]	values[5]	313	1			T64	12		T67	28		T352	8
auto[0]	values[3]	values[6]	318	1			T64	14		T179	8		T244	16
auto[0]	values[3]	values[7]	311	1			T243	2		T61	10		T212	24
auto[0]	values[4]	values[0]	299	1			T70	10		T59	12		T148	6
auto[0]	values[4]	values[1]	296	1			T190	6		T60	12		T59	8
auto[0]	values[4]	values[2]	200	1			T229	8		T66	10		T35	14
auto[0]	values[4]	values[3]	483	1			T42	44		T215	2		T64	9
auto[0]	values[4]	values[4]	230	1			T169	15		T254	23		T367	2
auto[0]	values[4]	values[5]	345	1			T250	10		T66	16		T67	12
auto[0]	values[4]	values[6]	238	1			T60	10		T99	16		T109	16
auto[0]	values[4]	values[7]	354	1			T212	26		T223	31		T240	13
auto[0]	values[5]	values[0]	162	1			T187	20		T220	6		T223	14
auto[0]	values[5]	values[1]	290	1			T58	14		T223	13		T358	16
auto[0]	values[5]	values[2]	356	1			T202	6		T204	12		T212	12
auto[0]	values[5]	values[3]	237	1			T99	13		T178	10		T236	15
auto[0]	values[5]	values[4]	355	1			T17	10		T239	2		T252	22
auto[0]	values[5]	values[5]	295	1			T212	39		T297	6		T218	12
auto[0]	values[5]	values[6]	134	1			T240	12		T281	15		T298	9
auto[0]	values[5]	values[7]	387	1			T188	10		T210	13		T347	4
auto[0]	values[6]	values[0]	295	1			T225	6		T66	20		T223	15
auto[0]	values[6]	values[1]	209	1			T99	10		T181	11		T368	18
auto[0]	values[6]	values[2]	340	1			T260	8		T212	10		T205	14
auto[0]	values[6]	values[3]	268	1			T59	17		T178	11		T142	8
auto[0]	values[6]	values[4]	319	1			T189	10		T181	8		T369	18
auto[0]	values[6]	values[5]	420	1			T64	13		T212	10		T251	4
auto[0]	values[6]	values[6]	273	1			T181	9		T210	4		T280	11
auto[0]	values[6]	values[7]	464	1			T59	12		T33	20		T207	14
auto[0]	values[7]	values[0]	284	1			T192	20		T242	2		T33	29
auto[0]	values[7]	values[1]	249	1			T23	2		T224	8		T61	9
auto[0]	values[7]	values[2]	223	1			T214	2		T66	18		T99	88
auto[0]	values[7]	values[3]	355	1			T59	13		T35	15		T61	30
auto[0]	values[7]	values[4]	190	1			T72	6		T264	11		T254	11
auto[0]	values[7]	values[5]	168	1			T16	10		T198	2		T180	7
auto[0]	values[7]	values[6]	316	1			T66	13		T67	16		T338	6
auto[0]	values[7]	values[7]	199	1			T91	14		T111	14		T59	26
auto[1]	values[0]	values[0]	123	1			T66	24		T277	24		T285	7
auto[1]	values[0]	values[1]	372	1			T99	11		T61	9		T236	9
auto[1]	values[0]	values[2]	99	1			T65	10		T61	9		T297	11
auto[1]	values[0]	values[3]	338	1			T61	25		T181	8		T146	14
auto[1]	values[0]	values[4]	155	1			T257	6		T212	28		T223	10
auto[1]	values[0]	values[5]	112	1			T169	4		T254	15		T218	20
auto[1]	values[0]	values[6]	136	1			T181	5		T205	6		T263	10
auto[1]	values[0]	values[7]	142	1			T253	11		T282	11		T173	11
auto[1]	values[1]	values[0]	186	1			T59	6		T181	3		T100	10
auto[1]	values[1]	values[1]	432	1			T99	10		T254	6		T266	7
auto[1]	values[1]	values[2]	183	1			T99	11		T61	11		T280	10
auto[1]	values[1]	values[3]	163	1			T64	4		T33	20		T245	18
auto[1]	values[1]	values[4]	187	1			T99	11		T280	10		T152	11
auto[1]	values[1]	values[5]	220	1			T223	11		T205	7		T253	14
auto[1]	values[1]	values[6]	163	1			T35	7		T61	10		T210	6
auto[1]	values[1]	values[7]	147	1			T142	7		T254	7		T218	8
auto[1]	values[2]	values[0]	175	1			T53	22		T210	15		T100	8
auto[1]	values[2]	values[1]	100	1			T66	9		T253	12		T313	1
auto[1]	values[2]	values[2]	135	1			T181	7		T210	9		T152	8
auto[1]	values[2]	values[3]	227	1			T33	17		T247	6		T66	9
auto[1]	values[2]	values[4]	140	1			T59	13		T212	11		T142	9
auto[1]	values[2]	values[5]	245	1			T57	8		T99	61		T199	12
auto[1]	values[2]	values[6]	364	1			T33	12		T210	8		T323	4
auto[1]	values[2]	values[7]	273	1			T35	39		T218	23		T263	21
auto[1]	values[3]	values[0]	315	1			T181	6		T210	8		T142	154
auto[1]	values[3]	values[1]	197	1			T210	10		T223	9		T254	5
auto[1]	values[3]	values[2]	160	1			T99	51		T181	12		T252	11
auto[1]	values[3]	values[3]	112	1			T99	15		T205	6		T282	20
auto[1]	values[3]	values[4]	219	1			T33	9		T180	14		T181	9
auto[1]	values[3]	values[5]	224	1			T64	8		T67	7		T236	8
auto[1]	values[3]	values[6]	410	1			T64	71		T223	10		T266	7
auto[1]	values[3]	values[7]	164	1			T61	10		T212	11		T142	5
auto[1]	values[4]	values[0]	120	1			T59	8		T313	6		T152	12
auto[1]	values[4]	values[1]	247	1			T60	8		T59	48		T100	12
auto[1]	values[4]	values[2]	209	1			T66	27		T35	7		T223	10
auto[1]	values[4]	values[3]	507	1			T64	168		T35	9		T99	82
auto[1]	values[4]	values[4]	167	1			T169	10		T254	10		T295	15
auto[1]	values[4]	values[5]	146	1			T66	4		T67	8		T264	10
auto[1]	values[4]	values[6]	194	1			T60	21		T99	4		T254	5
auto[1]	values[4]	values[7]	353	1			T212	6		T223	21		T240	11
auto[1]	values[5]	values[0]	162	1			T223	6		T240	43		T258	11
auto[1]	values[5]	values[1]	175	1			T223	7		T252	10		T100	8
auto[1]	values[5]	values[2]	357	1			T212	8		T181	12		T142	5
auto[1]	values[5]	values[3]	238	1			T99	7		T178	19		T236	5
auto[1]	values[5]	values[4]	143	1			T252	18		T274	11		T216	5
auto[1]	values[5]	values[5]	158	1			T212	11		T297	14		T218	8
auto[1]	values[5]	values[6]	178	1			T240	16		T281	53		T298	16
auto[1]	values[5]	values[7]	397	1			T210	7		T236	9		T142	23
auto[1]	values[6]	values[0]	156	1			T66	3		T223	12		T236	7
auto[1]	values[6]	values[1]	128	1			T114	18		T99	10		T181	9
auto[1]	values[6]	values[2]	118	1			T212	11		T205	10		T240	12
auto[1]	values[6]	values[3]	374	1			T6	24		T59	136		T178	9
auto[1]	values[6]	values[4]	216	1			T181	12		T297	8		T205	19
auto[1]	values[6]	values[5]	304	1			T64	19		T212	85		T181	4
auto[1]	values[6]	values[6]	187	1			T181	11		T210	16		T280	9
auto[1]	values[6]	values[7]	464	1			T59	50		T33	13		T252	8
auto[1]	values[7]	values[0]	260	1			T62	16		T33	20		T269	10
auto[1]	values[7]	values[1]	291	1			T61	37		T246	26		T230	20
auto[1]	values[7]	values[2]	215	1			T66	8		T99	10		T212	31
auto[1]	values[7]	values[3]	243	1			T59	23		T63	20		T35	5
auto[1]	values[7]	values[4]	113	1			T264	9		T254	9		T370	10
auto[1]	values[7]	values[5]	93	1			T180	17		T205	7		T266	5
auto[1]	values[7]	values[6]	218	1			T66	7		T67	4		T142	6
auto[1]	values[7]	values[7]	126	1			T59	11		T201	4		T181	7