Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	403	1			T8	4		T50	10		T56	4
auto[ReadAddrCrossIntoMailbox]	296	1			T56	4		T188	4		T59	3
auto[ReadAddrCrossOutOfMailbox]	290	1			T56	6		T188	4		T60	1
auto[ReadAddrCrossAllMailbox]	194	1			T56	2		T188	2		T191	2
auto[ReadAddrOutsideMailbox]	3615	1			T6	4		T17	2		T21	2

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2362

1

T6

2

T8

2

T17

1

auto[1]

2436

1

T6

2

T8

2

T17

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	834	1			T23	2		T50	2		T114	4
read_ops[0x0b]	778	1			T42	2		T50	2		T55	2
read_ops[0x3b]	816	1			T6	4		T70	2		T55	2
read_ops[0x6b]	841	1			T17	2		T21	2		T70	4
read_ops[0xbb]	785	1			T8	4		T50	2		T189	4
read_ops[0xeb]	744	1			T50	6		T56	4		T177	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T50	1		T61	1		T371	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	30	1			T50	1		T64	1		T371	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	31	1			T188	1		T64	2		T66	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	15	1			T188	1		T371	1		T180	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T188	2		T33	1		T349	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T188	2		T59	1		T64	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T188	1		T61	1		T223	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T188	1		T99	1		T252	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	321	1			T23	1		T114	2		T54	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	322	1			T23	1		T114	2		T54	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	31	1			T212	1		T181	1		T223	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	23	1			T33	1		T99	1		T61	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	29	1			T188	1		T64	1		T99	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	30	1			T188	1		T59	1		T61	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	20	1			T64	2		T242	1		T66	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	20	1			T242	1		T178	1		T181	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T178	1		T181	1		T205	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	10	1			T66	1		T254	1		T218	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	279	1			T42	1		T50	1		T55	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	321	1			T42	1		T50	1		T55	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	44	1			T189	2		T178	1		T223	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	36	1			T189	2		T33	1		T67	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T56	1		T59	2		T33	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T56	1		T33	1		T67	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	19	1			T56	1		T252	2		T148	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T56	1		T64	1		T33	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T198	1		T180	1		T223	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T198	1		T212	1		T236	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	297	1			T6	2		T70	1		T55	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	319	1			T6	2		T70	1		T55	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	28	1			T56	2		T64	1		T259	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T56	2		T259	1		T180	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T67	1		T100	1		T152	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T99	3		T178	2		T223	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	30	1			T56	1		T66	1		T181	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T56	1		T181	1		T210	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	21	1			T56	1		T218	1		T253	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	25	1			T56	1		T64	1		T61	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	300	1			T17	1		T21	1		T70	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	326	1			T17	1		T21	1		T70	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	31	1			T8	2		T50	1		T189	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T8	2		T50	1		T189	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	17	1			T61	1		T212	1		T252	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T212	1		T280	1		T252	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T60	1		T33	1		T61	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T67	1		T223	1		T252	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T181	1		T218	1		T263	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	10	1			T280	1		T315	1		T318	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	298	1			T191	2		T194	2		T62	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	304	1			T191	2		T194	2		T59	5
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	38	1			T50	3		T60	1		T33	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	42	1			T50	3		T259	6		T66	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T56	1		T33	1		T264	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	33	1			T56	1		T181	1		T210	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T56	1		T178	1		T181	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T56	1		T99	2		T252	2
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T191	1		T190	2		T178	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	11	1			T191	1		T190	2		T66	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	280	1			T177	1		T260	1		T60	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	248	1			T177	1		T260	1		T59	2