Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.32	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	1	127	99.22

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	1	127	99.22	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3837	1			T112	4		T107	12		T191	6
values[1]	4267	1			T16	10		T17	10		T73	20
values[2]	4007	1			T6	24		T72	6		T113	10
values[3]	3847	1			T85	8		T114	18		T189	10
values[4]	4891	1			T55	14		T57	8		T192	20
values[5]	3956	1			T50	14		T90	2		T188	10
values[6]	3906	1			T23	2		T91	14		T193	2
values[7]	3813	1			T8	6		T21	16		T42	44

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4654	1			T6	24		T21	16		T91	14
values[1]	4078	1			T8	6		T70	10		T111	14
values[2]	3246	1			T16	10		T17	10		T72	6
values[3]	4581	1			T56	20		T177	14		T58	14
values[4]	4041	1			T90	2		T193	2		T194	12
values[5]	4234	1			T112	4		T42	44		T53	22
values[6]	3675	1			T23	2		T55	14		T85	8
values[7]	4015	1			T50	14		T73	20		T188	10

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31711

1

T6

20

T8

6

T16

10

auto[1]

813

1

T6

4

T53

2

T60

2

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	1	127	99.22	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[5]]	[values[4]]	0	1	1

Covered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	499	1			T35	44		T99	26		T195	10
auto[0]	values[0]	values[1]	343	1			T191	6		T33	20		T169	25
auto[0]	values[0]	values[2]	581	1			T196	2		T197	2		T66	20
auto[0]	values[0]	values[3]	447	1			T198	2		T199	12		T200	10
auto[0]	values[0]	values[4]	604	1			T59	169		T180	23		T169	21
auto[0]	values[0]	values[5]	497	1			T112	4		T201	4		T35	20
auto[0]	values[0]	values[6]	276	1			T107	12		T60	29		T202	6
auto[0]	values[0]	values[7]	505	1			T203	6		T204	12		T99	18
auto[0]	values[1]	values[0]	712	1			T33	32		T35	60		T205	22
auto[0]	values[1]	values[1]	505	1			T206	8		T207	14		T99	64
auto[0]	values[1]	values[2]	284	1			T16	10		T17	10		T65	6
auto[0]	values[1]	values[3]	748	1			T58	14		T208	2		T209	16
auto[0]	values[1]	values[4]	333	1			T33	23		T66	20		T210	18
auto[0]	values[1]	values[5]	668	1			T211	2		T212	50		T213	12
auto[0]	values[1]	values[6]	524	1			T182	16		T214	2		T64	20
auto[0]	values[1]	values[7]	369	1			T73	20		T215	2		T62	12
auto[0]	values[2]	values[0]	253	1			T6	20		T113	10		T216	20
auto[0]	values[2]	values[1]	650	1			T87	6		T217	10		T212	37
auto[0]	values[2]	values[2]	389	1			T72	6		T218	103		T219	38
auto[0]	values[2]	values[3]	487	1			T56	20		T212	19		T142	20
auto[0]	values[2]	values[4]	507	1			T59	20		T110	6		T99	25
auto[0]	values[2]	values[5]	335	1			T220	6		T221	14		T222	6
auto[0]	values[2]	values[6]	556	1			T66	36		T99	20		T223	26
auto[0]	values[2]	values[7]	730	1			T64	83		T67	20		T99	119
auto[0]	values[3]	values[0]	534	1			T224	8		T225	6		T226	12
auto[0]	values[3]	values[1]	738	1			T64	84		T61	21		T223	31
auto[0]	values[3]	values[2]	386	1			T181	18		T227	8		T228	6
auto[0]	values[3]	values[3]	523	1			T229	8		T230	20		T223	20
auto[0]	values[3]	values[4]	497	1			T59	20		T35	18		T100	20
auto[0]	values[3]	values[5]	375	1			T59	37		T231	8		T232	8
auto[0]	values[3]	values[6]	541	1			T85	8		T114	18		T189	10
auto[0]	values[3]	values[7]	169	1			T233	20		T234	8		T235	6
auto[0]	values[4]	values[0]	740	1			T61	55		T223	45		T100	19
auto[0]	values[4]	values[1]	498	1			T59	62		T99	71		T236	20
auto[0]	values[4]	values[2]	427	1			T237	12		T152	20		T238	20
auto[0]	values[4]	values[3]	926	1			T66	23		T212	39		T239	2
auto[0]	values[4]	values[4]	532	1			T99	21		T181	39		T240	28
auto[0]	values[4]	values[5]	445	1			T57	8		T33	54		T241	12
auto[0]	values[4]	values[6]	620	1			T55	14		T192	20		T99	18
auto[0]	values[4]	values[7]	582	1			T242	2		T99	97		T142	25
auto[0]	values[5]	values[0]	798	1			T66	20		T243	2		T144	20
auto[0]	values[5]	values[1]	376	1			T111	14		T244	16		T245	27
auto[0]	values[5]	values[2]	413	1			T66	21		T180	21		T223	20
auto[0]	values[5]	values[3]	470	1			T59	53		T64	29		T246	24
auto[0]	values[5]	values[4]	194	1			T90	2		T194	12		T108	10
auto[0]	values[5]	values[5]	670	1			T187	20		T64	175		T247	6
auto[0]	values[5]	values[6]	385	1			T248	6		T59	20		T63	18
auto[0]	values[5]	values[7]	568	1			T50	14		T188	10		T249	12
auto[0]	values[6]	values[0]	520	1			T91	14		T250	10		T251	4
auto[0]	values[6]	values[1]	507	1			T60	20		T59	35		T33	20
auto[0]	values[6]	values[2]	231	1			T67	33		T252	19		T253	49
auto[0]	values[6]	values[3]	303	1			T177	14		T254	32		T205	19
auto[0]	values[6]	values[4]	796	1			T193	2		T255	6		T256	6
auto[0]	values[6]	values[5]	606	1			T257	6		T66	77		T61	45
auto[0]	values[6]	values[6]	383	1			T23	2		T61	32		T258	20
auto[0]	values[6]	values[7]	454	1			T54	22		T259	18		T109	16
auto[0]	values[7]	values[0]	491	1			T21	16		T260	8		T261	14
auto[0]	values[7]	values[1]	366	1			T8	6		T70	10		T83	34
auto[0]	values[7]	values[2]	449	1			T262	28		T263	25		T253	23
auto[0]	values[7]	values[3]	534	1			T264	58		T265	10		T266	20
auto[0]	values[7]	values[4]	497	1			T190	6		T35	19		T267	12
auto[0]	values[7]	values[5]	554	1			T42	44		T53	20		T59	20
auto[0]	values[7]	values[6]	302	1			T178	18		T212	20		T263	19
auto[0]	values[7]	values[7]	509	1			T35	19		T268	20		T269	20
auto[1]	values[0]	values[0]	7	1			T35	2		T236	2		T270	1
auto[1]	values[0]	values[1]	14	1			T271	5		T272	4		T273	1
auto[1]	values[0]	values[2]	15	1			T223	2		T252	4		T274	1
auto[1]	values[0]	values[3]	9	1			T181	4		T275	1		T276	2
auto[1]	values[0]	values[4]	13	1			T59	2		T180	1		T277	3
auto[1]	values[0]	values[5]	2	1			T278	2		-	-		-	-
auto[1]	values[0]	values[6]	8	1			T60	2		T178	1		T279	2
auto[1]	values[0]	values[7]	17	1			T99	2		T100	3		T152	1
auto[1]	values[1]	values[0]	23	1			T33	1		T35	1		T205	2
auto[1]	values[1]	values[1]	13	1			T99	1		T212	3		T280	2
auto[1]	values[1]	values[2]	9	1			T65	4		T66	1		T142	1
auto[1]	values[1]	values[3]	22	1			T100	5		T281	2		T282	1
auto[1]	values[1]	values[4]	8	1			T33	2		T210	2		T252	1
auto[1]	values[1]	values[5]	20	1			T100	3		T283	1		T284	1
auto[1]	values[1]	values[6]	11	1			T210	3		T100	1		T283	1
auto[1]	values[1]	values[7]	18	1			T62	4		T266	1		T277	3
auto[1]	values[2]	values[0]	12	1			T6	4		T285	3		T275	1
auto[1]	values[2]	values[1]	17	1			T181	3		T205	2		T271	2
auto[1]	values[2]	values[2]	7	1			T286	2		T287	1		T288	1
auto[1]	values[2]	values[3]	15	1			T212	2		T289	2		T290	2
auto[1]	values[2]	values[4]	13	1			T99	1		T100	4		T218	2
auto[1]	values[2]	values[5]	9	1			T222	2		T173	2		T291	2
auto[1]	values[2]	values[6]	11	1			T66	1		T223	1		T292	4
auto[1]	values[2]	values[7]	16	1			T205	1		T173	1		T293	3
auto[1]	values[3]	values[0]	3	1			T273	1		T294	2		-	-
auto[1]	values[3]	values[1]	10	1			T64	1		T223	1		T295	1
auto[1]	values[3]	values[2]	5	1			T181	2		T218	1		T296	2
auto[1]	values[3]	values[3]	19	1			T297	3		T205	1		T282	2
auto[1]	values[3]	values[4]	14	1			T35	3		T298	1		T299	6
auto[1]	values[3]	values[5]	10	1			T41	3		T300	4		T301	1
auto[1]	values[3]	values[6]	10	1			T142	2		T254	1		T302	2
auto[1]	values[3]	values[7]	13	1			T234	2		T303	3		T304	4
auto[1]	values[4]	values[0]	21	1			T61	2		T100	4		T152	1
auto[1]	values[4]	values[1]	8	1			T305	1		T306	1		T307	1
auto[1]	values[4]	values[2]	13	1			T281	1		T308	4		T291	2
auto[1]	values[4]	values[3]	35	1			T66	3		T212	1		T181	5
auto[1]	values[4]	values[4]	8	1			T99	3		T181	1		T295	1
auto[1]	values[4]	values[5]	6	1			T309	3		T300	1		T293	1
auto[1]	values[4]	values[6]	19	1			T99	2		T180	2		T100	1
auto[1]	values[4]	values[7]	11	1			T99	1		T142	2		T277	1
auto[1]	values[5]	values[0]	17	1			T310	1		T300	3		T286	3
auto[1]	values[5]	values[1]	10	1			T245	1		T254	1		T205	2
auto[1]	values[5]	values[2]	12	1			T180	3		T240	1		T282	1
auto[1]	values[5]	values[3]	16	1			T59	3		T64	3		T246	2
auto[1]	values[5]	values[5]	7	1			T64	2		T219	1		T311	1
auto[1]	values[5]	values[6]	9	1			T63	2		T100	1		T219	1
auto[1]	values[5]	values[7]	11	1			T181	1		T169	1		T312	1
auto[1]	values[6]	values[0]	10	1			T223	1		T218	2		T301	3
auto[1]	values[6]	values[1]	15	1			T59	1		T210	2		T223	1
auto[1]	values[6]	values[2]	10	1			T67	2		T252	1		T253	1
auto[1]	values[6]	values[3]	10	1			T254	1		T205	1		T41	2
auto[1]	values[6]	values[4]	20	1			T35	2		T313	2		T293	3
auto[1]	values[6]	values[5]	19	1			T61	1		T314	1		T315	3
auto[1]	values[6]	values[6]	9	1			T61	2		T281	1		T173	1
auto[1]	values[6]	values[7]	13	1			T218	2		T285	4		T316	2
auto[1]	values[7]	values[0]	14	1			T254	2		T312	2		T317	3
auto[1]	values[7]	values[1]	8	1			T269	2		T318	1		T319	2
auto[1]	values[7]	values[2]	15	1			T253	1		T320	1		T296	1
auto[1]	values[7]	values[3]	17	1			T264	3		T295	2		T219	2
auto[1]	values[7]	values[4]	5	1			T35	1		T321	2		T322	1
auto[1]	values[7]	values[5]	11	1			T53	2		T323	4		T302	1
auto[1]	values[7]	values[6]	11	1			T178	2		T263	1		T281	2
auto[1]	values[7]	values[7]	30	1			T35	1		T309	5		T152	1