Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	886	1			T9	15		T20	14		T97	10
all_values[1]	886	1			T9	15		T20	14		T97	10
all_values[2]	886	1			T9	15		T20	14		T97	10
all_values[3]	886	1			T9	15		T20	14		T97	10
all_values[4]	886	1			T9	15		T20	14		T97	10
all_values[5]	886	1			T9	15		T20	14		T97	10
all_values[6]	886	1			T9	15		T20	14		T97	10
all_values[7]	886	1			T9	15		T20	14		T97	10

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3837

1

T9

60

T20

72

T97

44

auto[1]

3251

1

T9

60

T20

40

T97

36

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2823

1

T9

50

T20

43

T97

28

auto[1]

4265

1

T9

70

T20

69

T97

52

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4021

1

T9

77

T20

63

T97

40

auto[1]

3067

1

T9

43

T20

49

T97

40

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	204	1			T9	5		T20	5		T97	4
all_values[0]	auto[0]	auto[0]	auto[1]	86	1			T9	2		T20	1		T175	1
all_values[0]	auto[0]	auto[1]	auto[0]	160	1			T9	4		T20	4		T97	2
all_values[0]	auto[0]	auto[1]	auto[1]	79	1			T32	2		T33	1		T34	1
all_values[0]	auto[1]	auto[0]	auto[1]	188	1			T9	1		T20	3		T97	1
all_values[0]	auto[1]	auto[1]	auto[1]	169	1			T9	3		T20	1		T97	3
all_values[1]	auto[0]	auto[0]	auto[0]	190	1			T9	2		T20	5		T97	4
all_values[1]	auto[0]	auto[0]	auto[1]	86	1			T9	3		T20	3		T32	3
all_values[1]	auto[0]	auto[1]	auto[0]	159	1			T9	1		T20	3		T97	1
all_values[1]	auto[0]	auto[1]	auto[1]	83	1			T9	4		T32	1		T176	1
all_values[1]	auto[1]	auto[0]	auto[1]	202	1			T9	3		T20	1		T97	2
all_values[1]	auto[1]	auto[1]	auto[1]	166	1			T9	2		T20	2		T97	3
all_values[2]	auto[0]	auto[0]	auto[0]	184	1			T9	4		T20	3		T97	3
all_values[2]	auto[0]	auto[0]	auto[1]	96	1			T9	2		T20	2		T32	2
all_values[2]	auto[0]	auto[1]	auto[0]	131	1			T9	2		T20	2		T97	2
all_values[2]	auto[0]	auto[1]	auto[1]	70	1			T20	1		T32	4		T33	1
all_values[2]	auto[1]	auto[0]	auto[1]	208	1			T9	4		T20	2		T97	5
all_values[2]	auto[1]	auto[1]	auto[1]	197	1			T9	3		T20	4		T32	10
all_values[3]	auto[0]	auto[0]	auto[0]	164	1			T9	3		T20	3		T32	7
all_values[3]	auto[0]	auto[0]	auto[1]	103	1			T9	3		T20	3		T97	2
all_values[3]	auto[0]	auto[1]	auto[0]	125	1			T9	4		T20	1		T32	4
all_values[3]	auto[0]	auto[1]	auto[1]	102	1			T9	1		T97	1		T32	1
all_values[3]	auto[1]	auto[0]	auto[1]	240	1			T9	2		T20	3		T97	5
all_values[3]	auto[1]	auto[1]	auto[1]	152	1			T9	2		T20	4		T97	2
all_values[4]	auto[0]	auto[0]	auto[0]	173	1			T9	2		T32	3		T33	1
all_values[4]	auto[0]	auto[0]	auto[1]	81	1			T9	2		T20	2		T97	1
all_values[4]	auto[0]	auto[1]	auto[0]	138	1			T9	3		T20	3		T97	1
all_values[4]	auto[0]	auto[1]	auto[1]	104	1			T9	2		T20	1		T97	3
all_values[4]	auto[1]	auto[0]	auto[1]	208	1			T9	5		T20	6		T97	3
all_values[4]	auto[1]	auto[1]	auto[1]	182	1			T9	1		T20	2		T97	2
all_values[5]	auto[0]	auto[0]	auto[0]	280	1			T9	4		T20	9		T32	13
all_values[5]	auto[0]	auto[1]	auto[0]	220	1			T9	6		T97	4		T32	6
all_values[5]	auto[1]	auto[0]	auto[1]	196	1			T9	2		T20	5		T97	2
all_values[5]	auto[1]	auto[1]	auto[1]	190	1			T9	3		T97	4		T32	1
all_values[6]	auto[0]	auto[0]	auto[0]	205	1			T9	1		T20	2		T97	3
all_values[6]	auto[0]	auto[0]	auto[1]	75	1			T20	3		T97	1		T32	2
all_values[6]	auto[0]	auto[1]	auto[0]	132	1			T9	5		T20	1		T97	2
all_values[6]	auto[0]	auto[1]	auto[1]	85	1			T9	4		T20	1		T97	1
all_values[6]	auto[1]	auto[0]	auto[1]	192	1			T9	1		T20	6		T97	1
all_values[6]	auto[1]	auto[1]	auto[1]	197	1			T9	4		T20	1		T97	2
all_values[7]	auto[0]	auto[0]	auto[0]	188	1			T9	3		T20	1		T97	2
all_values[7]	auto[0]	auto[0]	auto[1]	88	1			T9	2		T97	2		T32	2
all_values[7]	auto[0]	auto[1]	auto[0]	170	1			T9	1		T20	1		T32	6
all_values[7]	auto[0]	auto[1]	auto[1]	60	1			T9	2		T20	3		T97	1
all_values[7]	auto[1]	auto[0]	auto[1]	200	1			T9	4		T20	4		T97	3
all_values[7]	auto[1]	auto[1]	auto[1]	180	1			T9	3		T20	5		T97	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal