Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1691

1

T1

4

T4

5

T11

3

auto[1]

1801

1

T1

7

T4

5

T11

1

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1905

1

T11

3

T13

16

T45

10

auto[1]

1587

1

T1

11

T4

10

T11

1

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2770

1

T1

11

T4

10

T11

4

auto[1]

722

1

T13

8

T45

2

T46

1

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	708	1			T1	3		T4	2		T13	4
valid[1]	667	1			T1	2		T4	3		T11	1
valid[2]	680	1			T4	2		T11	1		T13	7
valid[3]	706	1			T1	1		T4	2		T11	2
valid[4]	731	1			T1	5		T4	1		T13	3

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	118	1			T45	1		T68	1		T105	1
auto[0]	auto[0]	valid[0]	auto[1]	138	1			T1	1		T25	2		T27	4
auto[0]	auto[0]	valid[1]	auto[0]	115	1			T13	1		T45	1		T105	1
auto[0]	auto[0]	valid[1]	auto[1]	137	1			T1	1		T4	2		T25	3
auto[0]	auto[0]	valid[2]	auto[0]	131	1			T11	1		T13	1		T395	3
auto[0]	auto[0]	valid[2]	auto[1]	152	1			T4	2		T14	1		T25	5
auto[0]	auto[0]	valid[3]	auto[0]	112	1			T11	1		T13	1		T45	1
auto[0]	auto[0]	valid[3]	auto[1]	157	1			T1	1		T11	1		T25	3
auto[0]	auto[0]	valid[4]	auto[0]	116	1			T13	1		T395	2		T392	1
auto[0]	auto[0]	valid[4]	auto[1]	161	1			T1	1		T4	1		T25	10
auto[0]	auto[1]	valid[0]	auto[0]	115	1			T13	1		T404	1		T395	1
auto[0]	auto[1]	valid[0]	auto[1]	187	1			T1	2		T4	2		T14	1
auto[0]	auto[1]	valid[1]	auto[0]	129	1			T11	1		T13	1		T45	1
auto[0]	auto[1]	valid[1]	auto[1]	147	1			T1	1		T4	1		T14	1
auto[0]	auto[1]	valid[2]	auto[0]	107	1			T13	2		T45	3		T395	2
auto[0]	auto[1]	valid[2]	auto[1]	160	1			T13	2		T14	1		T25	6
auto[0]	auto[1]	valid[3]	auto[0]	115	1			T45	1		T68	1		T395	1
auto[0]	auto[1]	valid[3]	auto[1]	165	1			T4	2		T25	4		T26	1
auto[0]	auto[1]	valid[4]	auto[0]	125	1			T395	3		T391	1		T60	1
auto[0]	auto[1]	valid[4]	auto[1]	183	1			T1	4		T14	1		T25	3
auto[1]	auto[0]	valid[0]	auto[0]	71	1			T13	1		T105	1		T385	1
auto[1]	auto[0]	valid[1]	auto[0]	70	1			T13	1		T45	1		T396	1
auto[1]	auto[0]	valid[2]	auto[0]	65	1			T13	1		T392	1		T84	1
auto[1]	auto[0]	valid[3]	auto[0]	72	1			T68	1		T105	1		T60	1
auto[1]	auto[0]	valid[4]	auto[0]	76	1			T13	2		T46	1		T380	1
auto[1]	auto[1]	valid[0]	auto[0]	79	1			T13	2		T68	1		T105	1
auto[1]	auto[1]	valid[1]	auto[0]	69	1			T45	1		T105	1		T32	3
auto[1]	auto[1]	valid[2]	auto[0]	65	1			T13	1		T395	2		T392	1
auto[1]	auto[1]	valid[3]	auto[0]	85	1			T68	2		T395	2		T60	1
auto[1]	auto[1]	valid[4]	auto[0]	70	1			T395	1		T380	1		T84	2

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal