Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48363

1

T5

14

T11

122

T13

367

auto[1]

16593

1

T1

11

T4

10

T11

30

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47071

1

T1

11

T4

10

T5

6

auto[1]

17885

1

T5

8

T11

51

T13

142

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	33247	1			T1	11		T4	10		T5	6
others[1]	5515	1			T11	9		T13	33		T25	44
others[2]	5541	1			T5	1		T11	10		T13	38
others[3]	6242	1			T5	2		T11	14		T13	51
interest[1]	3576	1			T5	1		T11	8		T13	18
interest[4]	21694	1			T1	11		T4	10		T5	4
interest[64]	10835	1			T5	4		T11	28		T13	63

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	15517	1			T5	1		T11	39		T13	120
auto[0]	auto[0]	others[1]	2560	1			T11	6		T13	18		T38	1
auto[0]	auto[0]	others[2]	2546	1			T11	4		T13	20		T45	22
auto[0]	auto[0]	others[3]	2962	1			T5	1		T11	8		T13	26
auto[0]	auto[0]	interest[1]	1711	1			T11	6		T13	9		T45	10
auto[0]	auto[0]	interest[4]	10088	1			T5	1		T11	24		T13	68
auto[0]	auto[0]	interest[64]	5182	1			T5	4		T11	8		T13	32
auto[0]	auto[1]	others[0]	8582	1			T1	11		T4	10		T11	16
auto[0]	auto[1]	others[1]	1438	1			T13	2		T25	44		T27	41
auto[0]	auto[1]	others[2]	1376	1			T11	2		T13	6		T25	31
auto[0]	auto[1]	others[3]	1575	1			T11	3		T13	6		T25	48
auto[0]	auto[1]	interest[1]	900	1			T11	2		T25	28		T27	23
auto[0]	auto[1]	interest[4]	5711	1			T1	11		T4	10		T11	8
auto[0]	auto[1]	interest[64]	2722	1			T11	7		T13	10		T25	94
auto[1]	auto[0]	others[0]	9148	1			T5	5		T11	28		T13	68
auto[1]	auto[0]	others[1]	1517	1			T11	3		T13	13		T45	10
auto[1]	auto[0]	others[2]	1619	1			T5	1		T11	4		T13	12
auto[1]	auto[0]	others[3]	1705	1			T5	1		T11	3		T13	19
auto[1]	auto[0]	interest[1]	965	1			T5	1		T13	9		T15	2
auto[1]	auto[0]	interest[4]	5895	1			T5	3		T11	21		T13	45
auto[1]	auto[0]	interest[64]	2931	1			T11	13		T13	21		T15	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal