Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3021651	1			T1	1		T3	1		T4	1
all_values[1]	3021651	1			T1	1		T3	1		T4	1
all_values[2]	3021651	1			T1	1		T3	1		T4	1
all_values[3]	3021651	1			T1	1		T3	1		T4	1
all_values[4]	3021651	1			T1	1		T3	1		T4	1
all_values[5]	3021651	1			T1	1		T3	1		T4	1
all_values[6]	3021651	1			T1	1		T3	1		T4	1
all_values[7]	3021651	1			T1	1		T3	1		T4	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24039491

1

T1

8

T3

8

T4

8

auto[1]

133717

1

T32

66

T33

22

T34

19861

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24141593

1

T1

8

T3

8

T4

8

auto[1]

31615

1

T41

1

T44

144

T88

104

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2989272	1			T1	1		T3	1		T4	1
all_values[0]	auto[0]	auto[1]	14687	1			T41	1		T44	58		T88	52
all_values[0]	auto[1]	auto[0]	17226	1			T32	2		T33	3		T34	4
all_values[0]	auto[1]	auto[1]	466	1			T32	1		T33	1		T34	5
all_values[1]	auto[0]	auto[0]	3004458	1			T1	1		T3	1		T4	1
all_values[1]	auto[0]	auto[1]	10128	1			T44	57		T88	52		T23	213
all_values[1]	auto[1]	auto[0]	6812	1			T32	7		T34	6541		T35	3
all_values[1]	auto[1]	auto[1]	253	1			T32	5		T33	1		T34	67
all_values[2]	auto[0]	auto[0]	2998896	1			T1	1		T3	1		T4	1
all_values[2]	auto[0]	auto[1]	3926	1			T44	29		T23	82		T191	8
all_values[2]	auto[1]	auto[0]	18619	1			T32	4		T33	2		T34	6590
all_values[2]	auto[1]	auto[1]	210	1			T32	4		T33	1		T34	13
all_values[3]	auto[0]	auto[0]	2981646	1			T1	1		T3	1		T4	1
all_values[3]	auto[0]	auto[1]	225	1			T32	2		T33	3		T34	2
all_values[3]	auto[1]	auto[0]	39594	1			T32	7		T33	3		T34	6603
all_values[3]	auto[1]	auto[1]	186	1			T32	2		T34	4		T85	2
all_values[4]	auto[0]	auto[0]	2998480	1			T1	1		T3	1		T4	1
all_values[4]	auto[0]	auto[1]	190	1			T168	2		T32	3		T33	2
all_values[4]	auto[1]	auto[0]	22778	1			T32	8		T33	4		T34	9
all_values[4]	auto[1]	auto[1]	203	1			T32	5		T33	2		T34	3
all_values[5]	auto[0]	auto[0]	3020347	1			T1	1		T3	1		T4	1
all_values[5]	auto[0]	auto[1]	196	1			T32	3		T33	2		T34	2
all_values[5]	auto[1]	auto[0]	948	1			T32	8		T33	1		T34	8
all_values[5]	auto[1]	auto[1]	160	1			T32	2		T33	1		T34	1
all_values[6]	auto[0]	auto[0]	2995657	1			T1	1		T3	1		T4	1
all_values[6]	auto[0]	auto[1]	204	1			T32	3		T33	2		T34	5
all_values[6]	auto[1]	auto[0]	25612	1			T32	2		T33	2		T34	5
all_values[6]	auto[1]	auto[1]	178	1			T32	4		T34	2		T85	3
all_values[7]	auto[0]	auto[0]	3020973	1			T1	1		T3	1		T4	1
all_values[7]	auto[0]	auto[1]	206	1			T32	4		T33	3		T34	4
all_values[7]	auto[1]	auto[0]	275	1			T32	4		T34	4		T35	2
all_values[7]	auto[1]	auto[1]	197	1			T32	1		T33	1		T34	2