Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.04 98.38 94.01 98.62 89.36 97.19 95.45 99.26


Total tests in report: 1131
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
61.20 61.20 92.25 92.25 78.27 78.27 60.43 60.43 24.44 24.44 88.52 88.52 71.69 71.69 12.77 12.77 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_pass_addr_payload_swap.203693147
75.52 14.32 95.98 3.73 85.66 7.39 63.29 2.85 77.78 53.33 93.56 5.04 81.51 9.82 30.84 18.07 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_and_tpm.1826640386
80.86 5.34 96.52 0.54 88.82 3.16 86.71 23.43 82.22 4.44 94.66 1.10 81.65 0.14 35.45 4.60 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_mode_ignore_cmds.457368863
84.65 3.79 96.91 0.39 89.85 1.03 88.98 2.26 82.22 0.00 95.08 0.42 81.93 0.28 57.57 22.13 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_stress_all.23632621
87.52 2.88 98.04 1.13 91.44 1.59 91.14 2.17 88.89 6.67 96.70 1.62 84.92 2.99 61.53 3.96 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_all.1724628067
89.13 1.61 98.04 0.00 91.56 0.11 91.93 0.79 88.89 0.00 96.74 0.03 93.60 8.68 63.17 1.63 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2187547207
90.72 1.59 98.09 0.06 91.67 0.11 91.93 0.00 88.89 0.00 96.87 0.14 93.60 0.00 73.96 10.79 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_stress_all.169436146
91.47 0.75 98.19 0.09 91.78 0.11 91.93 0.00 93.33 4.44 96.97 0.10 93.60 0.00 74.46 0.50 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_intercept.2009005352
92.14 0.68 98.21 0.02 91.78 0.00 96.65 4.72 93.33 0.00 96.97 0.00 93.60 0.00 74.46 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_ram_cfg.4186388876
92.81 0.67 98.21 0.00 91.82 0.04 96.65 0.00 93.33 0.00 96.97 0.00 93.60 0.00 79.11 4.65 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_and_tpm.4187275754
93.39 0.58 98.23 0.02 91.84 0.02 96.65 0.00 93.33 0.00 96.97 0.00 93.60 0.00 83.12 4.01 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_stress_all.2028154670
93.73 0.34 98.23 0.00 91.84 0.00 96.65 0.00 93.33 0.00 96.97 0.00 93.74 0.14 85.35 2.23 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_stress_all.174400740
94.05 0.32 98.23 0.01 91.88 0.04 98.43 1.77 93.33 0.00 96.99 0.02 93.88 0.14 85.59 0.25 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_sec_cm.1444092592
94.32 0.28 98.23 0.00 91.88 0.00 98.43 0.00 93.33 0.00 96.99 0.00 93.88 0.00 87.52 1.93 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_and_tpm_min_idle.2593247297
94.54 0.21 98.35 0.11 92.55 0.67 98.43 0.00 93.33 0.00 97.14 0.15 94.45 0.57 87.52 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_read_buffer_direct.2813339935
94.74 0.21 98.35 0.00 92.55 0.00 98.43 0.00 93.33 0.00 97.14 0.00 94.45 0.00 88.96 1.44 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_and_tpm.2643637433
94.94 0.19 98.35 0.00 92.55 0.00 98.43 0.00 93.33 0.00 97.14 0.00 94.45 0.00 90.30 1.34 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_and_tpm_min_idle.1056580234
95.09 0.15 98.36 0.01 92.66 0.11 98.43 0.00 93.33 0.00 97.16 0.02 94.45 0.00 91.24 0.94 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.3907047021
95.24 0.15 98.36 0.00 92.68 0.01 98.43 0.00 93.33 0.00 97.16 0.00 94.45 0.00 92.28 1.04 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_read_hw_reg.3723934417
95.38 0.14 98.36 0.00 92.68 0.00 98.43 0.00 93.33 0.00 97.16 0.00 95.45 1.00 92.28 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_rw.1368115575
95.52 0.14 98.36 0.00 92.68 0.00 98.43 0.00 93.33 0.00 97.16 0.00 95.45 0.00 93.27 0.99 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_and_tpm.1595622677
95.66 0.13 98.36 0.00 92.68 0.00 98.43 0.00 93.33 0.00 97.16 0.00 95.45 0.00 94.21 0.94 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_all.1096445298
95.79 0.13 98.36 0.00 93.38 0.71 98.43 0.00 93.33 0.00 97.16 0.00 95.45 0.00 94.41 0.20 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_errors.3022479324
95.89 0.10 98.36 0.00 93.41 0.02 98.43 0.00 93.33 0.00 97.18 0.02 95.45 0.00 95.10 0.69 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_mode_ignore_cmds.2657690805
95.98 0.08 98.36 0.00 93.41 0.00 98.43 0.00 93.33 0.00 97.18 0.00 95.45 0.00 95.69 0.59 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_and_tpm.1457106697
96.05 0.07 98.36 0.00 93.41 0.00 98.43 0.00 93.33 0.00 97.18 0.00 95.45 0.00 96.19 0.50 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_and_tpm_min_idle.640341347
96.10 0.06 98.36 0.00 93.41 0.00 98.43 0.00 93.33 0.00 97.18 0.00 95.45 0.00 96.58 0.40 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_mode_ignore_cmds.3345802875
96.15 0.05 98.36 0.00 93.41 0.00 98.43 0.00 93.33 0.00 97.18 0.00 95.45 0.00 96.93 0.35 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_and_tpm_min_idle.2319537859
96.20 0.05 98.36 0.00 93.41 0.00 98.43 0.00 93.33 0.00 97.18 0.00 95.45 0.00 97.28 0.35 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_mode_ignore_cmds.3061644596
96.25 0.04 98.36 0.00 93.41 0.00 98.43 0.00 93.33 0.00 97.18 0.00 95.45 0.00 97.57 0.30 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_mode.883371232
96.29 0.04 98.36 0.00 93.69 0.29 98.43 0.00 93.33 0.00 97.18 0.00 95.45 0.00 97.57 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_mailbox.398588970
96.33 0.04 98.36 0.00 93.76 0.06 98.43 0.00 93.33 0.00 97.19 0.02 95.45 0.00 97.77 0.20 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_mode_ignore_cmds.1989076625
96.36 0.04 98.38 0.03 93.79 0.04 98.62 0.20 93.33 0.00 97.19 0.00 95.45 0.00 97.77 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_alert_test.2145809029
96.39 0.03 98.38 0.00 93.91 0.11 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 97.87 0.10 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_errors.2713889187
96.42 0.03 98.38 0.00 93.91 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 98.07 0.20 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_stress_all.1660632793
96.45 0.03 98.38 0.00 93.91 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 98.27 0.20 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_mode_ignore_cmds.606709376
96.47 0.02 98.38 0.00 93.91 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 98.42 0.15 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_intg_err.1750673704
96.49 0.02 98.38 0.00 93.91 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 98.56 0.15 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_and_tpm.3447844655
96.51 0.01 98.38 0.00 93.91 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 98.66 0.10 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_mode_ignore_cmds.2747841187
96.52 0.01 98.38 0.00 93.91 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 98.76 0.10 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_and_tpm_min_idle.3895356658
96.54 0.01 98.38 0.00 93.91 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 98.86 0.10 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_stress_all.3840471002
96.54 0.01 98.38 0.00 93.92 0.01 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 98.91 0.05 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_intg_err.2306624384
96.55 0.01 98.38 0.00 93.92 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 98.96 0.05 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_intg_err.739673328
96.56 0.01 98.38 0.00 93.92 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 99.01 0.05 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_mailbox.3289725703
96.57 0.01 98.38 0.00 93.92 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 99.06 0.05 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_stress_all.2876891860
96.57 0.01 98.38 0.00 93.92 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 99.11 0.05 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_mode.1071959016
96.58 0.01 98.38 0.00 93.92 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 99.16 0.05 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_and_tpm_min_idle.334545559
96.59 0.01 98.38 0.00 93.92 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 99.21 0.05 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_mode_ignore_cmds.148666824
96.59 0.01 98.38 0.00 93.92 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 99.26 0.05 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_mode.1565889999
96.60 0.01 98.38 0.00 93.96 0.04 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 99.26 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_errors.4231743120
96.60 0.01 98.38 0.00 93.98 0.02 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 99.26 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2421195451
96.60 0.01 98.38 0.00 93.99 0.01 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 99.26 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_csb_read.1003249054
96.61 0.01 98.38 0.00 94.01 0.01 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 99.26 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_and_tpm_min_idle.917958204

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.1769674453
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.936425599
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.3146174190
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.3878601168
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.2268894849
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.2468397394
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.670334406
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.1087031330
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.2281004718
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1877672741
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.4235544938
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3111030677
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.2044886647
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.2764897711
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.1288075686
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.1847580673
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.50896403
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.2866605862
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.2918884772
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1839499975
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_rw.2656702049
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_intr_test.1990657863
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.220860847
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_errors.1043120508
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_intg_err.863059000
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2393821367
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_rw.546758615
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_intr_test.2350380614
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2604196016
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_intg_err.1111752309
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2828927
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_rw.2530826670
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_intr_test.2779567445
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1170385894
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_errors.403715182
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/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_all.2006260452
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_read_hw_reg.2465525895
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_rw.649655720
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_sts_read.3758157127
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_upload.4085308857
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_alert_test.1197122239
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_cfg_cmd.1226138451
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_csb_read.1385903985
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_all.3376287669
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/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_sts_read.873039829
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_upload.632125241
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_alert_test.365917339
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_cfg_cmd.2631709984
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_csb_read.162041693
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_all.2697936515
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_and_tpm.3965456434
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_mode_ignore_cmds.750873007
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_intercept.1036992603
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_mailbox.3974887042
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.3745322290
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_pass_cmd_filtering.2224367225
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_read_buffer_direct.722588558
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_stress_all.1532472842
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_all.732751145
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_read_hw_reg.3523996086
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/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_sts_read.533558031
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_upload.3789029735
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_alert_test.4224782270
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_cfg_cmd.675191507
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_csb_read.409514402
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_all.3615602554
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_and_tpm.1206838631
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_and_tpm_min_idle.3617023331
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_mode.3642663711
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.2416148872
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_intercept.1799502096
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/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_cfg_cmd.854175974
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_csb_read.1502037638
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_all.83825871
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_and_tpm_min_idle.2902603803
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_mode.287310379
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_mode_ignore_cmds.1247701432
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_intercept.2364765985
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_mailbox.2797885737
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.2002568425
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.4187643616
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.2812067955
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_stress_all.3266607715
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_all.2201124956
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.1526978130
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_rw.2771867660
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.1221255630
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_upload.3341071685



Total test records in report: 1131
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_csb_read.1003249054 Aug 27 06:07:28 PM UTC 24 Aug 27 06:07:31 PM UTC 24 125942029 ps
T2 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_sec_cm.395952853 Aug 27 06:12:10 PM UTC 24 Aug 27 06:12:13 PM UTC 24 312756247 ps
T3 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_ram_cfg.4186388876 Aug 27 06:07:32 PM UTC 24 Aug 27 06:07:34 PM UTC 24 46976619 ps
T4 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_sts_read.2261436736 Aug 27 06:07:35 PM UTC 24 Aug 27 06:07:37 PM UTC 24 21365635 ps
T5 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_rw.261573891 Aug 27 06:07:38 PM UTC 24 Aug 27 06:07:40 PM UTC 24 13225914 ps
T6 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_all.654822270 Aug 27 06:07:35 PM UTC 24 Aug 27 06:07:42 PM UTC 24 1438326648 ps
T7 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_pass_cmd_filtering.1797538171 Aug 27 06:07:41 PM UTC 24 Aug 27 06:07:49 PM UTC 24 430390217 ps
T8 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_read_hw_reg.508382647 Aug 27 06:07:35 PM UTC 24 Aug 27 06:07:51 PM UTC 24 6872485204 ps
T9 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_pass_addr_payload_swap.203693147 Aug 27 06:07:42 PM UTC 24 Aug 27 06:08:05 PM UTC 24 2776335257 ps
T10 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_cfg_cmd.2184688680 Aug 27 06:07:56 PM UTC 24 Aug 27 06:08:07 PM UTC 24 1928879861 ps
T11 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_mailbox.3289725703 Aug 27 06:07:52 PM UTC 24 Aug 27 06:08:15 PM UTC 24 4229431808 ps
T12 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_read_buffer_direct.3813392750 Aug 27 06:08:07 PM UTC 24 Aug 27 06:08:23 PM UTC 24 7183843311 ps
T13 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_mode_ignore_cmds.457368863 Aug 27 06:08:06 PM UTC 24 Aug 27 06:08:26 PM UTC 24 1616509982 ps
T14 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_intercept.2009005352 Aug 27 06:07:50 PM UTC 24 Aug 27 06:08:32 PM UTC 24 6943503252 ps
T15 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_mode.1021634247 Aug 27 06:08:03 PM UTC 24 Aug 27 06:08:34 PM UTC 24 4571852161 ps
T16 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_sec_cm.1444092592 Aug 27 06:08:33 PM UTC 24 Aug 27 06:08:35 PM UTC 24 808624267 ps
T90 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_alert_test.2145809029 Aug 27 06:08:36 PM UTC 24 Aug 27 06:08:38 PM UTC 24 11869010 ps
T17 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_csb_read.1318856621 Aug 27 06:08:37 PM UTC 24 Aug 27 06:08:39 PM UTC 24 19747796 ps
T24 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_all.1724628067 Aug 27 06:08:42 PM UTC 24 Aug 27 06:08:53 PM UTC 24 1243285490 ps
T25 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_sts_read.738391918 Aug 27 06:08:54 PM UTC 24 Aug 27 06:08:57 PM UTC 24 217662045 ps
T26 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_rw.1369753078 Aug 27 06:08:57 PM UTC 24 Aug 27 06:09:00 PM UTC 24 42262640 ps
T27 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_read_hw_reg.3723934417 Aug 27 06:08:40 PM UTC 24 Aug 27 06:09:06 PM UTC 24 3808159082 ps
T18 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_upload.3389995484 Aug 27 06:07:54 PM UTC 24 Aug 27 06:09:07 PM UTC 24 46920697143 ps
T19 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_pass_addr_payload_swap.2708296951 Aug 27 06:09:07 PM UTC 24 Aug 27 06:09:12 PM UTC 24 1321124539 ps
T69 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_intercept.4139426479 Aug 27 06:09:09 PM UTC 24 Aug 27 06:09:17 PM UTC 24 256627498 ps
T53 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_pass_cmd_filtering.1332680058 Aug 27 06:09:00 PM UTC 24 Aug 27 06:09:26 PM UTC 24 7600096046 ps
T56 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_cfg_cmd.2846492293 Aug 27 06:09:27 PM UTC 24 Aug 27 06:09:31 PM UTC 24 242855877 ps
T117 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_mode.2524172660 Aug 27 06:09:32 PM UTC 24 Aug 27 06:09:44 PM UTC 24 410274078 ps
T118 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_mailbox.398588970 Aug 27 06:09:13 PM UTC 24 Aug 27 06:09:45 PM UTC 24 2828845178 ps
T54 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_upload.2961724824 Aug 27 06:09:18 PM UTC 24 Aug 27 06:09:49 PM UTC 24 7761516533 ps
T45 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_read_buffer_direct.2813339935 Aug 27 06:09:44 PM UTC 24 Aug 27 06:09:52 PM UTC 24 546356587 ps
T20 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_sec_cm.1571634900 Aug 27 06:09:54 PM UTC 24 Aug 27 06:09:57 PM UTC 24 84107355 ps
T91 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_alert_test.4113587566 Aug 27 06:09:58 PM UTC 24 Aug 27 06:10:00 PM UTC 24 60782768 ps
T28 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_csb_read.1726517236 Aug 27 06:09:59 PM UTC 24 Aug 27 06:10:01 PM UTC 24 45852078 ps
T29 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_read_hw_reg.3141334423 Aug 27 06:10:01 PM UTC 24 Aug 27 06:10:06 PM UTC 24 442222524 ps
T30 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_sts_read.2969950647 Aug 27 06:10:05 PM UTC 24 Aug 27 06:10:07 PM UTC 24 352220499 ps
T31 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_rw.3060863394 Aug 27 06:10:07 PM UTC 24 Aug 27 06:10:11 PM UTC 24 88957912 ps
T215 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_pass_cmd_filtering.1401110231 Aug 27 06:10:08 PM UTC 24 Aug 27 06:10:12 PM UTC 24 36971998 ps
T270 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_intercept.721242209 Aug 27 06:10:09 PM UTC 24 Aug 27 06:10:14 PM UTC 24 63970800 ps
T55 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_pass_addr_payload_swap.372841431 Aug 27 06:10:08 PM UTC 24 Aug 27 06:10:15 PM UTC 24 224012688 ps
T65 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_upload.1849919540 Aug 27 06:10:13 PM UTC 24 Aug 27 06:10:19 PM UTC 24 368976605 ps
T47 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_mode.4131828344 Aug 27 06:10:15 PM UTC 24 Aug 27 06:10:20 PM UTC 24 159812934 ps
T36 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_all.3429509237 Aug 27 06:10:02 PM UTC 24 Aug 27 06:10:22 PM UTC 24 1324975330 ps
T57 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_cfg_cmd.3118806503 Aug 27 06:10:15 PM UTC 24 Aug 27 06:10:36 PM UTC 24 1077736864 ps
T66 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_mailbox.966098633 Aug 27 06:10:11 PM UTC 24 Aug 27 06:10:39 PM UTC 24 4920417424 ps
T21 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_sec_cm.4064513536 Aug 27 06:10:37 PM UTC 24 Aug 27 06:10:40 PM UTC 24 81906496 ps
T46 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_read_buffer_direct.2559863589 Aug 27 06:10:21 PM UTC 24 Aug 27 06:10:40 PM UTC 24 1591742385 ps
T52 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_mode.1781308486 Aug 27 06:11:54 PM UTC 24 Aug 27 06:12:08 PM UTC 24 959441894 ps
T378 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_csb_read.1252996900 Aug 27 06:10:40 PM UTC 24 Aug 27 06:10:42 PM UTC 24 89819302 ps
T92 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_alert_test.1416992641 Aug 27 06:10:40 PM UTC 24 Aug 27 06:10:42 PM UTC 24 13671657 ps
T67 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_sts_read.1767218056 Aug 27 06:10:44 PM UTC 24 Aug 27 06:10:46 PM UTC 24 114872493 ps
T41 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_and_tpm.1826640386 Aug 27 06:09:45 PM UTC 24 Aug 27 06:10:50 PM UTC 24 3905834078 ps
T40 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_mode_ignore_cmds.2747841187 Aug 27 06:09:42 PM UTC 24 Aug 27 06:10:50 PM UTC 24 16556125645 ps
T42 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_all.1715022286 Aug 27 06:10:44 PM UTC 24 Aug 27 06:10:51 PM UTC 24 591673635 ps
T43 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_rw.4042812510 Aug 27 06:10:47 PM UTC 24 Aug 27 06:10:52 PM UTC 24 536595326 ps
T105 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_read_hw_reg.276332512 Aug 27 06:10:44 PM UTC 24 Aug 27 06:10:57 PM UTC 24 983197473 ps
T106 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_intercept.3149965839 Aug 27 06:10:52 PM UTC 24 Aug 27 06:10:57 PM UTC 24 134589532 ps
T107 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_pass_addr_payload_swap.3687940539 Aug 27 06:10:51 PM UTC 24 Aug 27 06:10:58 PM UTC 24 258971972 ps
T108 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_mode.2534193988 Aug 27 06:10:59 PM UTC 24 Aug 27 06:11:08 PM UTC 24 1573547554 ps
T109 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_read_buffer_direct.4030303485 Aug 27 06:11:09 PM UTC 24 Aug 27 06:11:17 PM UTC 24 991065326 ps
T110 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_upload.3525570409 Aug 27 06:10:57 PM UTC 24 Aug 27 06:11:20 PM UTC 24 949354688 ps
T119 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_cfg_cmd.1104018497 Aug 27 06:10:58 PM UTC 24 Aug 27 06:11:30 PM UTC 24 2653543495 ps
T59 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_all.2625026109 Aug 27 06:11:11 PM UTC 24 Aug 27 06:11:32 PM UTC 24 4650492798 ps
T22 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_sec_cm.1140317782 Aug 27 06:11:31 PM UTC 24 Aug 27 06:11:34 PM UTC 24 115700545 ps
T379 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_alert_test.74066430 Aug 27 06:11:34 PM UTC 24 Aug 27 06:11:36 PM UTC 24 11772434 ps
T380 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_csb_read.2421815215 Aug 27 06:11:36 PM UTC 24 Aug 27 06:11:38 PM UTC 24 15201464 ps
T44 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_and_tpm.1457106697 Aug 27 06:08:15 PM UTC 24 Aug 27 06:11:43 PM UTC 24 20507066468 ps
T244 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_pass_cmd_filtering.3438749686 Aug 27 06:10:51 PM UTC 24 Aug 27 06:11:45 PM UTC 24 54057898609 ps
T381 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_sts_read.3292129218 Aug 27 06:11:44 PM UTC 24 Aug 27 06:11:46 PM UTC 24 185652374 ps
T216 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_mailbox.3934670336 Aug 27 06:10:53 PM UTC 24 Aug 27 06:11:49 PM UTC 24 9413126036 ps
T68 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_rw.2723670228 Aug 27 06:11:45 PM UTC 24 Aug 27 06:11:49 PM UTC 24 146575190 ps
T48 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_and_tpm_min_idle.4059888858 Aug 27 06:09:51 PM UTC 24 Aug 27 06:11:51 PM UTC 24 29619688001 ps
T382 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_pass_addr_payload_swap.4026185024 Aug 27 06:11:49 PM UTC 24 Aug 27 06:11:53 PM UTC 24 51731028 ps
T51 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_all.1335274763 Aug 27 06:10:23 PM UTC 24 Aug 27 06:12:01 PM UTC 24 22865448186 ps
T383 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_read_hw_reg.3467073252 Aug 27 06:11:39 PM UTC 24 Aug 27 06:12:02 PM UTC 24 7143300314 ps
T211 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_cfg_cmd.1503988692 Aug 27 06:11:54 PM UTC 24 Aug 27 06:12:02 PM UTC 24 623177588 ps
T60 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_pass_cmd_filtering.1024700394 Aug 27 06:11:47 PM UTC 24 Aug 27 06:12:03 PM UTC 24 2971899460 ps
T384 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_alert_test.498082580 Aug 27 06:12:10 PM UTC 24 Aug 27 06:12:12 PM UTC 24 13618692 ps
T111 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_read_buffer_direct.1069272196 Aug 27 06:12:02 PM UTC 24 Aug 27 06:12:09 PM UTC 24 337542977 ps
T88 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_and_tpm.4142840934 Aug 27 06:10:24 PM UTC 24 Aug 27 06:12:12 PM UTC 24 21777135019 ps
T385 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.1221255630 Aug 27 06:13:54 PM UTC 24 Aug 27 06:13:56 PM UTC 24 32484466 ps
T386 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_csb_read.1520447606 Aug 27 06:12:13 PM UTC 24 Aug 27 06:12:15 PM UTC 24 47452938 ps
T387 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_sts_read.3758157127 Aug 27 06:12:16 PM UTC 24 Aug 27 06:12:19 PM UTC 24 91739334 ps
T226 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_intercept.3564918166 Aug 27 06:11:49 PM UTC 24 Aug 27 06:12:20 PM UTC 24 2760734172 ps
T369 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_rw.649655720 Aug 27 06:12:16 PM UTC 24 Aug 27 06:12:20 PM UTC 24 184249732 ps
T251 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_upload.1337853986 Aug 27 06:11:53 PM UTC 24 Aug 27 06:12:24 PM UTC 24 11749766560 ps
T62 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_pass_addr_payload_swap.541591535 Aug 27 06:12:20 PM UTC 24 Aug 27 06:12:27 PM UTC 24 1464904725 ps
T368 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_all.1530201398 Aug 27 06:11:40 PM UTC 24 Aug 27 06:12:27 PM UTC 24 72955368851 ps
T23 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_stress_all.2028154670 Aug 27 06:09:51 PM UTC 24 Aug 27 06:12:28 PM UTC 24 24973025880 ps
T263 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_pass_cmd_filtering.1918245376 Aug 27 06:12:20 PM UTC 24 Aug 27 06:12:29 PM UTC 24 417108630 ps
T63 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_and_tpm_min_idle.2825300344 Aug 27 06:11:21 PM UTC 24 Aug 27 06:12:31 PM UTC 24 18142964442 ps
T212 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_cfg_cmd.3650646700 Aug 27 06:12:27 PM UTC 24 Aug 27 06:12:31 PM UTC 24 75397868 ps
T388 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_mailbox.2910011090 Aug 27 06:12:21 PM UTC 24 Aug 27 06:12:36 PM UTC 24 994332292 ps
T389 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_read_hw_reg.2465525895 Aug 27 06:12:14 PM UTC 24 Aug 27 06:12:37 PM UTC 24 4019271126 ps
T89 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_mode_ignore_cmds.1760173059 Aug 27 06:10:19 PM UTC 24 Aug 27 06:12:38 PM UTC 24 17826428012 ps
T61 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_upload.4085308857 Aug 27 06:12:25 PM UTC 24 Aug 27 06:12:39 PM UTC 24 1053365368 ps
T390 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_alert_test.2464667761 Aug 27 06:12:39 PM UTC 24 Aug 27 06:12:41 PM UTC 24 15563244 ps
T391 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_csb_read.1385903985 Aug 27 06:12:40 PM UTC 24 Aug 27 06:12:42 PM UTC 24 27183649 ps
T361 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_all.2104629123 Aug 27 06:13:32 PM UTC 24 Aug 27 06:13:55 PM UTC 24 9477133360 ps
T268 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_mailbox.2682490404 Aug 27 06:11:53 PM UTC 24 Aug 27 06:12:45 PM UTC 24 19427434026 ps
T163 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_read_buffer_direct.2715938596 Aug 27 06:12:29 PM UTC 24 Aug 27 06:12:46 PM UTC 24 2603186003 ps
T360 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_all.2006260452 Aug 27 06:12:14 PM UTC 24 Aug 27 06:12:46 PM UTC 24 40201676899 ps
T392 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_sts_read.873039829 Aug 27 06:12:45 PM UTC 24 Aug 27 06:12:48 PM UTC 24 73287192 ps
T393 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_rw.2943633710 Aug 27 06:12:46 PM UTC 24 Aug 27 06:12:48 PM UTC 24 46564943 ps
T164 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_mode.64840563 Aug 27 06:12:28 PM UTC 24 Aug 27 06:12:48 PM UTC 24 4602945801 ps
T394 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_pass_addr_payload_swap.3711761430 Aug 27 06:12:47 PM UTC 24 Aug 27 06:12:51 PM UTC 24 34755697 ps
T198 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_pass_cmd_filtering.1992112414 Aug 27 06:12:47 PM UTC 24 Aug 27 06:12:56 PM UTC 24 8020866043 ps
T395 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_read_hw_reg.8860325 Aug 27 06:12:42 PM UTC 24 Aug 27 06:12:58 PM UTC 24 1232500709 ps
T120 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_intercept.3808665199 Aug 27 06:12:21 PM UTC 24 Aug 27 06:12:58 PM UTC 24 14896248904 ps
T317 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_cfg_cmd.1226138451 Aug 27 06:12:49 PM UTC 24 Aug 27 06:12:59 PM UTC 24 1042331986 ps
T359 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_all.2630824280 Aug 27 06:12:43 PM UTC 24 Aug 27 06:13:01 PM UTC 24 1242610367 ps
T49 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_all.4169996960 Aug 27 06:08:09 PM UTC 24 Aug 27 06:13:01 PM UTC 24 25719609066 ps
T396 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_all.3376287669 Aug 27 06:12:59 PM UTC 24 Aug 27 06:13:01 PM UTC 24 48408975 ps
T220 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_upload.632125241 Aug 27 06:12:49 PM UTC 24 Aug 27 06:13:01 PM UTC 24 3492733878 ps
T269 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_intercept.867217142 Aug 27 06:12:48 PM UTC 24 Aug 27 06:13:02 PM UTC 24 1376867983 ps
T165 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_read_buffer_direct.2234773894 Aug 27 06:12:59 PM UTC 24 Aug 27 06:13:03 PM UTC 24 316212483 ps
T397 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_alert_test.1197122239 Aug 27 06:13:02 PM UTC 24 Aug 27 06:13:04 PM UTC 24 46653228 ps
T371 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_rw.2771867660 Aug 27 06:13:54 PM UTC 24 Aug 27 06:13:56 PM UTC 24 206957145 ps
T398 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_csb_read.162041693 Aug 27 06:13:02 PM UTC 24 Aug 27 06:13:05 PM UTC 24 15522312 ps
T399 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_sts_read.533558031 Aug 27 06:13:06 PM UTC 24 Aug 27 06:13:08 PM UTC 24 58875024 ps
T374 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_rw.2576641828 Aug 27 06:13:06 PM UTC 24 Aug 27 06:13:10 PM UTC 24 509445129 ps
T400 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_read_hw_reg.3523996086 Aug 27 06:13:02 PM UTC 24 Aug 27 06:13:10 PM UTC 24 382769588 ps
T401 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.3745322290 Aug 27 06:13:07 PM UTC 24 Aug 27 06:13:11 PM UTC 24 125119546 ps
T104 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_all.1574949848 Aug 27 06:12:03 PM UTC 24 Aug 27 06:13:15 PM UTC 24 21014954038 ps
T219 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_upload.3789029735 Aug 27 06:13:10 PM UTC 24 Aug 27 06:13:18 PM UTC 24 315557236 ps
T50 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_intercept.1036992603 Aug 27 06:13:09 PM UTC 24 Aug 27 06:13:19 PM UTC 24 222905150 ps
T58 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_mode_ignore_cmds.1989076625 Aug 27 06:12:01 PM UTC 24 Aug 27 06:13:21 PM UTC 24 3282082119 ps
T273 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_cfg_cmd.2631709984 Aug 27 06:13:13 PM UTC 24 Aug 27 06:13:24 PM UTC 24 1130247546 ps
T266 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_pass_cmd_filtering.2224367225 Aug 27 06:13:06 PM UTC 24 Aug 27 06:13:26 PM UTC 24 3013901303 ps
T166 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_mode.883371232 Aug 27 06:13:16 PM UTC 24 Aug 27 06:13:27 PM UTC 24 146903311 ps
T96 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_all.2844977173 Aug 27 06:09:45 PM UTC 24 Aug 27 06:13:28 PM UTC 24 42169309378 ps
T402 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_alert_test.365917339 Aug 27 06:13:28 PM UTC 24 Aug 27 06:13:30 PM UTC 24 13385674 ps
T167 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_read_buffer_direct.722588558 Aug 27 06:13:19 PM UTC 24 Aug 27 06:13:30 PM UTC 24 999821807 ps
T403 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_csb_read.409514402 Aug 27 06:13:29 PM UTC 24 Aug 27 06:13:31 PM UTC 24 63513689 ps
T283 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_mailbox.184865148 Aug 27 06:12:49 PM UTC 24 Aug 27 06:13:31 PM UTC 24 4923773738 ps
T191 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_and_tpm_min_idle.4132771928 Aug 27 06:12:38 PM UTC 24 Aug 27 06:13:32 PM UTC 24 16843973808 ps
T168 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_mode.3642663711 Aug 27 06:13:41 PM UTC 24 Aug 27 06:14:00 PM UTC 24 511134940 ps
T370 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_all.732751145 Aug 27 06:13:05 PM UTC 24 Aug 27 06:13:33 PM UTC 24 1781571457 ps
T245 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_and_tpm.2910150813 Aug 27 06:12:33 PM UTC 24 Aug 27 06:13:34 PM UTC 24 9026312131 ps
T404 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_read_hw_reg.4214466171 Aug 27 06:13:31 PM UTC 24 Aug 27 06:13:34 PM UTC 24 772900323 ps
T405 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_sts_read.2586361658 Aug 27 06:13:32 PM UTC 24 Aug 27 06:13:34 PM UTC 24 75996645 ps
T406 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_rw.2883191844 Aug 27 06:13:33 PM UTC 24 Aug 27 06:13:35 PM UTC 24 11392580 ps
T276 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_cfg_cmd.675191507 Aug 27 06:13:36 PM UTC 24 Aug 27 06:13:40 PM UTC 24 33788555 ps
T275 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_mailbox.3974887042 Aug 27 06:13:10 PM UTC 24 Aug 27 06:13:40 PM UTC 24 1605015024 ps
T237 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_intercept.1799502096 Aug 27 06:13:36 PM UTC 24 Aug 27 06:13:41 PM UTC 24 114373103 ps
T197 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_and_tpm_min_idle.3703940758 Aug 27 06:13:01 PM UTC 24 Aug 27 06:13:43 PM UTC 24 1878696150 ps
T253 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_pass_addr_payload_swap.946637623 Aug 27 06:13:34 PM UTC 24 Aug 27 06:13:43 PM UTC 24 517783715 ps
T210 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_mode_ignore_cmds.4192022475 Aug 27 06:12:57 PM UTC 24 Aug 27 06:13:46 PM UTC 24 9001318090 ps
T407 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_read_buffer_direct.4286144608 Aug 27 06:13:42 PM UTC 24 Aug 27 06:13:48 PM UTC 24 76042234 ps
T243 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_upload.3216219116 Aug 27 06:13:36 PM UTC 24 Aug 27 06:13:48 PM UTC 24 2186147746 ps
T208 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.2416148872 Aug 27 06:13:41 PM UTC 24 Aug 27 06:13:49 PM UTC 24 2341139997 ps
T264 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_and_tpm.3933097734 Aug 27 06:12:03 PM UTC 24 Aug 27 06:13:51 PM UTC 24 8396465719 ps
T408 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_alert_test.4224782270 Aug 27 06:13:50 PM UTC 24 Aug 27 06:13:52 PM UTC 24 14476703 ps
T409 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_csb_read.1502037638 Aug 27 06:13:50 PM UTC 24 Aug 27 06:13:52 PM UTC 24 38085699 ps
T32 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_stress_all.169436146 Aug 27 06:10:28 PM UTC 24 Aug 27 06:13:53 PM UTC 24 26824355224 ps
T350 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_mode.2034665940 Aug 27 06:12:52 PM UTC 24 Aug 27 06:13:59 PM UTC 24 2965159230 ps
T299 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.2002568425 Aug 27 06:13:57 PM UTC 24 Aug 27 06:14:03 PM UTC 24 426057653 ps
T227 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_all.2697936515 Aug 27 06:13:20 PM UTC 24 Aug 27 06:14:03 PM UTC 24 5285738780 ps
T240 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_upload.3341071685 Aug 27 06:14:01 PM UTC 24 Aug 27 06:14:07 PM UTC 24 288057113 ps
T285 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_cfg_cmd.854175974 Aug 27 06:14:04 PM UTC 24 Aug 27 06:14:08 PM UTC 24 71094138 ps
T365 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_all.2201124956 Aug 27 06:13:53 PM UTC 24 Aug 27 06:14:09 PM UTC 24 1214809521 ps
T372 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_all.1071595229 Aug 27 06:15:18 PM UTC 24 Aug 27 06:15:54 PM UTC 24 16035941605 ps
T277 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_intercept.2364765985 Aug 27 06:13:57 PM UTC 24 Aug 27 06:14:12 PM UTC 24 1349005160 ps
T410 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_all.83825871 Aug 27 06:14:10 PM UTC 24 Aug 27 06:14:12 PM UTC 24 17554766 ps
T411 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_mode.287310379 Aug 27 06:14:04 PM UTC 24 Aug 27 06:14:12 PM UTC 24 1089687110 ps
T412 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.1526978130 Aug 27 06:13:53 PM UTC 24 Aug 27 06:14:16 PM UTC 24 16418210939 ps
T33 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_stress_all.3266607715 Aug 27 06:14:13 PM UTC 24 Aug 27 06:14:16 PM UTC 24 66963974 ps
T97 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_all.2200861083 Aug 27 06:12:32 PM UTC 24 Aug 27 06:14:18 PM UTC 24 41743252938 ps
T182 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_alert_test.4010691534 Aug 27 06:14:18 PM UTC 24 Aug 27 06:14:20 PM UTC 24 11752631 ps
T183 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_csb_read.4077261309 Aug 27 06:14:18 PM UTC 24 Aug 27 06:14:20 PM UTC 24 52705059 ps
T184 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.2812067955 Aug 27 06:14:09 PM UTC 24 Aug 27 06:14:20 PM UTC 24 1690129228 ps
T185 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_mailbox.2797885737 Aug 27 06:14:01 PM UTC 24 Aug 27 06:14:21 PM UTC 24 1828313271 ps
T186 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.4187643616 Aug 27 06:13:56 PM UTC 24 Aug 27 06:14:22 PM UTC 24 46773466763 ps
T187 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_sts_read.408157339 Aug 27 06:14:21 PM UTC 24 Aug 27 06:14:23 PM UTC 24 178923744 ps
T188 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_and_tpm.1206838631 Aug 27 06:13:44 PM UTC 24 Aug 27 06:14:27 PM UTC 24 3738643681 ps
T189 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_rw.2895253163 Aug 27 06:14:22 PM UTC 24 Aug 27 06:14:27 PM UTC 24 82301049 ps
T303 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_pass_addr_payload_swap.4251627251 Aug 27 06:14:23 PM UTC 24 Aug 27 06:14:33 PM UTC 24 4219632379 ps
T413 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_read_hw_reg.126012601 Aug 27 06:14:21 PM UTC 24 Aug 27 06:14:37 PM UTC 24 4919737600 ps
T259 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_mailbox.1736351827 Aug 27 06:14:27 PM UTC 24 Aug 27 06:14:37 PM UTC 24 281151313 ps
T230 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_upload.1035548883 Aug 27 06:14:28 PM UTC 24 Aug 27 06:14:42 PM UTC 24 6506262351 ps
T267 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_mode.2859039032 Aug 27 06:14:38 PM UTC 24 Aug 27 06:14:42 PM UTC 24 36254186 ps
T194 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_pass_cmd_filtering.1665201227 Aug 27 06:13:34 PM UTC 24 Aug 27 06:14:43 PM UTC 24 10890406128 ps
T34 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_stress_all.23632621 Aug 27 06:08:27 PM UTC 24 Aug 27 06:14:44 PM UTC 24 115643239725 ps
T373 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_all.4047296179 Aug 27 06:14:21 PM UTC 24 Aug 27 06:14:48 PM UTC 24 6885525527 ps
T278 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_mailbox.3346145354 Aug 27 06:13:36 PM UTC 24 Aug 27 06:14:50 PM UTC 24 5705348999 ps
T414 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_alert_test.3447091703 Aug 27 06:14:49 PM UTC 24 Aug 27 06:14:51 PM UTC 24 20359119 ps
T257 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_intercept.4103455032 Aug 27 06:14:24 PM UTC 24 Aug 27 06:14:52 PM UTC 24 1991411940 ps
T415 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_read_buffer_direct.3851837457 Aug 27 06:14:43 PM UTC 24 Aug 27 06:14:52 PM UTC 24 8417718077 ps
T416 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_csb_read.3737420637 Aug 27 06:14:51 PM UTC 24 Aug 27 06:14:53 PM UTC 24 49239614 ps
T417 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_sts_read.719809241 Aug 27 06:14:53 PM UTC 24 Aug 27 06:14:55 PM UTC 24 117139873 ps
T316 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_cfg_cmd.379149103 Aug 27 06:14:34 PM UTC 24 Aug 27 06:14:57 PM UTC 24 3493715059 ps
T418 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_rw.249330617 Aug 27 06:14:54 PM UTC 24 Aug 27 06:14:57 PM UTC 24 219600169 ps
T254 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_and_tpm.3965456434 Aug 27 06:13:21 PM UTC 24 Aug 27 06:15:01 PM UTC 24 6176887728 ps
T419 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_read_hw_reg.1235374899 Aug 27 06:14:53 PM UTC 24 Aug 27 06:15:02 PM UTC 24 2603211397 ps
T209 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_mode_ignore_cmds.2709067205 Aug 27 06:14:38 PM UTC 24 Aug 27 06:15:03 PM UTC 24 743612359 ps
T271 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_upload.4209178722 Aug 27 06:15:02 PM UTC 24 Aug 27 06:15:07 PM UTC 24 54906397 ps
T238 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_intercept.1631048013 Aug 27 06:14:58 PM UTC 24 Aug 27 06:15:08 PM UTC 24 220090153 ps
T291 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_mailbox.1527064924 Aug 27 06:15:02 PM UTC 24 Aug 27 06:15:08 PM UTC 24 528599154 ps
T282 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_pass_cmd_filtering.568308531 Aug 27 06:14:22 PM UTC 24 Aug 27 06:15:09 PM UTC 24 20897671744 ps
T258 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_pass_cmd_filtering.2170073903 Aug 27 06:14:56 PM UTC 24 Aug 27 06:15:10 PM UTC 24 2800566032 ps
T324 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_cfg_cmd.861491727 Aug 27 06:15:04 PM UTC 24 Aug 27 06:15:12 PM UTC 24 695253176 ps
T64 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_all.3615602554 Aug 27 06:13:44 PM UTC 24 Aug 27 06:15:12 PM UTC 24 6379888903 ps
T298 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_pass_addr_payload_swap.558496219 Aug 27 06:14:57 PM UTC 24 Aug 27 06:15:14 PM UTC 24 7581130039 ps
T420 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_read_buffer_direct.1361580828 Aug 27 06:15:09 PM UTC 24 Aug 27 06:15:15 PM UTC 24 105662301 ps
T421 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_alert_test.1446556690 Aug 27 06:15:13 PM UTC 24 Aug 27 06:15:16 PM UTC 24 96359550 ps
T35 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_stress_all.1532472842 Aug 27 06:13:28 PM UTC 24 Aug 27 06:15:16 PM UTC 24 6733499663 ps
T422 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_csb_read.3396704932 Aug 27 06:15:15 PM UTC 24 Aug 27 06:15:17 PM UTC 24 67075825 ps
T195 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_and_tpm_min_idle.1056580234 Aug 27 06:13:24 PM UTC 24 Aug 27 06:15:17 PM UTC 24 3744287574 ps
T242 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_intercept.2425360268 Aug 27 06:15:45 PM UTC 24 Aug 27 06:15:51 PM UTC 24 95939420 ps
T367 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_and_tpm_min_idle.1359593784 Aug 27 06:15:10 PM UTC 24 Aug 27 06:15:18 PM UTC 24 870544344 ps
T423 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_sts_read.2098603646 Aug 27 06:15:18 PM UTC 24 Aug 27 06:15:20 PM UTC 24 121401515 ps
T424 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_rw.3010877976 Aug 27 06:15:18 PM UTC 24 Aug 27 06:15:21 PM UTC 24 105417517 ps
T362 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_all.2540073546 Aug 27 06:14:53 PM UTC 24 Aug 27 06:15:21 PM UTC 24 16087826317 ps
T98 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_mode_ignore_cmds.1247701432 Aug 27 06:14:08 PM UTC 24 Aug 27 06:15:21 PM UTC 24 15801309038 ps
T192 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_mode_ignore_cmds.639706667 Aug 27 06:10:59 PM UTC 24 Aug 27 06:15:22 PM UTC 24 44844166331 ps
T425 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_read_hw_reg.1318618320 Aug 27 06:15:17 PM UTC 24 Aug 27 06:15:24 PM UTC 24 1370412504 ps
T280 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_pass_cmd_filtering.237100263 Aug 27 06:15:19 PM UTC 24 Aug 27 06:15:27 PM UTC 24 2265665730 ps
T426 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_upload.3451766584 Aug 27 06:15:23 PM UTC 24 Aug 27 06:15:28 PM UTC 24 717840282 ps
T261 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_intercept.1972955205 Aug 27 06:15:21 PM UTC 24 Aug 27 06:15:28 PM UTC 24 209535126 ps
T307 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_pass_addr_payload_swap.3370902501 Aug 27 06:15:19 PM UTC 24 Aug 27 06:15:29 PM UTC 24 7204828836 ps
T427 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_mode.1269602873 Aug 27 06:15:23 PM UTC 24 Aug 27 06:15:31 PM UTC 24 185424682 ps
T193 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_and_tpm.4187275754 Aug 27 06:13:00 PM UTC 24 Aug 27 06:15:33 PM UTC 24 11541617550 ps
T428 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_mode.1354848360 Aug 27 06:15:09 PM UTC 24 Aug 27 06:15:34 PM UTC 24 1385313594 ps
T429 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_alert_test.1529092381 Aug 27 06:15:34 PM UTC 24 Aug 27 06:15:36 PM UTC 24 35273226 ps
T295 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_cfg_cmd.3267923296 Aug 27 06:15:23 PM UTC 24 Aug 27 06:15:38 PM UTC 24 3368666780 ps
T430 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_csb_read.1830617639 Aug 27 06:15:35 PM UTC 24 Aug 27 06:15:38 PM UTC 24 24804062 ps
T431 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_read_hw_reg.1402407708 Aug 27 06:15:39 PM UTC 24 Aug 27 06:15:41 PM UTC 24 25541531 ps
T213 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_all.2097423181 Aug 27 06:15:09 PM UTC 24 Aug 27 06:15:41 PM UTC 24 5331908748 ps
T432 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_sts_read.1351692527 Aug 27 06:15:41 PM UTC 24 Aug 27 06:15:43 PM UTC 24 58130837 ps
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T434 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_read_buffer_direct.1418539708 Aug 27 06:15:28 PM UTC 24 Aug 27 06:15:47 PM UTC 24 1239762818 ps
T196 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_and_tpm_min_idle.2593247297 Aug 27 06:10:26 PM UTC 24 Aug 27 06:15:48 PM UTC 24 59612599736 ps
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T85 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_stress_all.2876891860 Aug 27 06:15:12 PM UTC 24 Aug 27 06:15:59 PM UTC 24 6643204811 ps
T86 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_alert_test.3799875514 Aug 27 06:15:58 PM UTC 24 Aug 27 06:16:00 PM UTC 24 11390346 ps
T87 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_csb_read.3744202300 Aug 27 06:15:58 PM UTC 24 Aug 27 06:16:01 PM UTC 24 51624664 ps
T37 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_and_tpm_min_idle.917958204 Aug 27 06:08:24 PM UTC 24 Aug 27 06:16:02 PM UTC 24 304182333478 ps
T435 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_sts_read.4026853461 Aug 27 06:16:02 PM UTC 24 Aug 27 06:16:04 PM UTC 24 75209016 ps
T436 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_rw.3298091092 Aug 27 06:16:02 PM UTC 24 Aug 27 06:16:05 PM UTC 24 29962472 ps
T311 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_mailbox.3460159033 Aug 27 06:15:48 PM UTC 24 Aug 27 06:16:06 PM UTC 24 822567107 ps
T231 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_pass_addr_payload_swap.3297966792 Aug 27 06:15:44 PM UTC 24 Aug 27 06:16:08 PM UTC 24 3585627710 ps
T437 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_read_buffer_direct.2901384604 Aug 27 06:15:54 PM UTC 24 Aug 27 06:16:08 PM UTC 24 15590871687 ps
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