Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	35687	1			T7	2		T9	6		T10	8
auto[SpiFlashAddrCfg]	8422	1			T7	2		T9	4		T13	10
auto[SpiFlashAddr3b]	9919	1			T7	2		T9	6		T11	6
auto[SpiFlashAddr4b]	8307	1			T13	13		T15	2		T19	6

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34980

1

T7

6

T10

8

T11

6

auto[1]

27355

1

T9

16

T13

32

T19

14

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33317

1

T7

4

T9

12

T10

8

auto[1]

29018

1

T7

2

T9

4

T11

6

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	40701	1			T7	2		T9	16		T10	8
values[1]	1274	1			T13	3		T14	4		T41	5
values[2]	1533	1			T13	2		T41	4		T40	5
values[3]	1578	1			T13	6		T53	2		T41	5
values[4]	1640	1			T13	2		T54	2		T52	3
values[5]	1539	1			T13	2		T19	2		T53	4
values[6]	1640	1			T7	2		T13	9		T19	2
values[7]	1600	1			T13	3		T14	2		T53	2
values[8]	10830	1			T7	2		T11	6		T13	14

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34845

1

T7

6

T9

16

T10

8

auto[1]

27490

1

T13

80

T15

2

T47

1

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

58898

1

T7

6

T9

16

T10

8

write

3437

1

T13

5

T18

2

T55

2

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

21063

1

T7

2

T10

8

T11

4

valids[0x1]

41272

1

T7

4

T9

16

T11

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1696	1			T9	2		T13	2		T41	2
internal_process_ops[0x5a]	1704	1			T9	6		T13	9		T14	4
internal_process_ops[0x05]	20531	1			T7	2		T13	4		T69	2
internal_process_ops[0x35]	1688	1			T9	4		T13	1		T19	4
internal_process_ops[0x15]	1733	1			T13	2		T19	2		T41	3
internal_process_ops[0x03]	1160	1			T13	1		T18	6		T54	2
internal_process_ops[0x0b]	1158	1			T9	4		T11	2		T14	2
internal_process_ops[0x3b]	1151	1			T47	1		T52	2		T41	5
internal_process_ops[0x6b]	1201	1			T11	4		T53	2		T54	4
internal_process_ops[0xbb]	1167	1			T13	1		T19	2		T41	4
internal_process_ops[0xeb]	1290	1			T14	4		T19	2		T53	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

60627

1

T7

6

T9

16

T10

8

auto[1]

1708

1

T13

3

T55

2

T41

16

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

59802

1

T7

6

T9

16

T10

8

auto[1]

2533

1

T13

3

T41

15

T40

15

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11398

1

T7

2

T10

8

T69

2

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7217

1

T9

6

T19

6

T55

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2358

1

T7

2

T14

4

T18

8

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

2109

1

T9

4

T55

4

T41

8

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2798

1

T7

2

T11

6

T14

6

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2501

1

T9

6

T19

2

T55

4

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2452

1

T41

9

T59

2

T44

8

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

2164

1

T19

6

T41

9

T59

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

137

1

T44

1

T48

1

T63

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

92

1

T41

2

T63

2

T191

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

95

1

T32

2

T192

2

T193

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

116

1

T41

2

T59

1

T44

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

123

1

T44

2

T32

2

T194

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

100

1

T44

1

T195

4

T196

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

113

1

T63

2

T49

1

T58

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

127

1

T41

7

T49

3

T58

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

127

1

T18

2

T48

1

T58

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

113

1

T49

1

T58

2

T32

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

131

1

T41

2

T44

1

T58

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

126

1

T41

3

T34

2

T195

4

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

141

1

T44

2

T58

1

T195

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

118

1

T41

1

T44

1

T63

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

75

1

T48

1

T64

1

T195

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

114

1

T55

2

T41

1

T62

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9426

1

T13

21

T40

56

T51

30

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6820

1

T13

8

T40

19

T51

76

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1517

1

T13

2

T40

15

T51

10

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1556

1

T13

8

T40

7

T51

9

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1813

1

T13

15

T52

3

T40

15

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1918

1

T13

9

T40

29

T51

15

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1469

1

T13

7

T15

2

T47

1

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1382

1

T13

5

T40

11

T51

8

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

72

1

T13

1

T40

2

T51

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

114

1

T13

1

T40

2

T89

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

106

1

T13

1

T40

5

T23

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

94

1

T88

1

T23

3

T104

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

103

1

T51

2

T23

1

T104

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

102

1

T23

1

T89

2

T104

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

91

1

T88

1

T23

1

T89

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

123

1

T23

5

T104

1

T197

4

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

86

1

T89

3

T96

2

T197

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

107

1

T40

2

T51

1

T23

4

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

120

1

T88

1

T23

3

T89

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

79

1

T13

1

T40

2

T51

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

119

1

T23

2

T104

3

T96

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

95

1

T13

1

T40

2

T23

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

90

1

T23

3

T89

1

T197

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

88

1

T40

4

T23

1

T104

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	4437	1			T10	8		T56	6		T57	6
auto[0]	values[0]	valids[0x1]	17539	1			T7	2		T9	16		T18	4
auto[0]	values[1]	valids[0x1]	734	1			T14	4		T41	5		T110	2
auto[0]	values[2]	valids[0x0]	575	1			T41	3		T63	2		T49	4
auto[0]	values[2]	valids[0x1]	320	1			T41	1		T48	2		T198	2
auto[0]	values[3]	valids[0x0]	637	1			T53	2		T41	4		T59	3
auto[0]	values[3]	valids[0x1]	333	1			T41	1		T106	2		T59	1
auto[0]	values[4]	valids[0x0]	640	1			T41	2		T110	2		T44	6
auto[0]	values[4]	valids[0x1]	324	1			T54	2		T44	1		T49	2
auto[0]	values[5]	valids[0x0]	601	1			T19	2		T41	4		T59	1
auto[0]	values[5]	valids[0x1]	331	1			T53	4		T41	1		T62	2
auto[0]	values[6]	valids[0x0]	640	1			T7	2		T19	2		T41	4
auto[0]	values[6]	valids[0x1]	348	1			T41	1		T44	2		T48	2
auto[0]	values[7]	valids[0x0]	607	1			T53	2		T41	4		T48	1
auto[0]	values[7]	valids[0x1]	345	1			T14	2		T55	2		T44	3
auto[0]	values[8]	valids[0x0]	4145	1			T11	4		T14	4		T18	2
auto[0]	values[8]	valids[0x1]	2289	1			T7	2		T11	2		T18	6
auto[1]	values[0]	valids[0x0]	3940	1			T13	14		T40	35		T51	24
auto[1]	values[0]	valids[0x1]	14785	1			T13	25		T15	2		T40	68
auto[1]	values[1]	valids[0x1]	540	1			T13	3		T40	11		T51	7
auto[1]	values[2]	valids[0x0]	399	1			T13	2		T40	3		T51	1
auto[1]	values[2]	valids[0x1]	239	1			T40	2		T51	2		T89	1
auto[1]	values[3]	valids[0x0]	366	1			T13	4		T40	3		T51	2
auto[1]	values[3]	valids[0x1]	242	1			T13	2		T40	1		T51	4
auto[1]	values[4]	valids[0x0]	384	1			T13	1		T52	2		T40	6
auto[1]	values[4]	valids[0x1]	292	1			T13	1		T52	1		T40	1
auto[1]	values[5]	valids[0x0]	346	1			T40	6		T23	6		T89	2
auto[1]	values[5]	valids[0x1]	261	1			T13	2		T40	3		T51	4
auto[1]	values[6]	valids[0x0]	410	1			T13	5		T40	3		T23	5
auto[1]	values[6]	valids[0x1]	242	1			T13	4		T40	2		T51	3
auto[1]	values[7]	valids[0x0]	393	1			T13	1		T40	2		T51	1
auto[1]	values[7]	valids[0x1]	255	1			T13	2		T51	1		T23	11
auto[1]	values[8]	valids[0x0]	2543	1			T13	8		T47	1		T40	13
auto[1]	values[8]	valids[0x1]	1853	1			T13	6		T40	21		T51	7