Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3758126

1

T7

1

T9

1

T10

1891

auto[1]

29588

1

T13

34

T41

244

T40

127

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1020702

1

T7

1

T9

1

T10

1891

auto[1]

2767012

1

T13

2437

T69

256

T54

256

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	663446	1			T7	1		T9	1		T10	4
auto[524288:1048575]	446957	1			T10	956		T11	170		T14	3470
auto[1048576:1572863]	426706	1			T10	8		T13	933		T14	53
auto[1572864:2097151]	450786	1			T11	391		T13	27		T14	763
auto[2097152:2621439]	429797	1			T11	217		T13	547		T14	20
auto[2621440:3145727]	485260	1			T11	14		T13	37		T14	392
auto[3145728:3670015]	441294	1			T11	3		T13	516		T14	1388
auto[3670016:4194303]	443468	1			T10	923		T11	58		T14	3315

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2804488

1

T7

1

T9

1

T10

11

auto[1]

983226

1

T10

1880

T11

893

T14

10219

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3261286

1

T7

1

T9

1

T10

6

auto[1]

526428

1

T10

1885

T13

522

T56

1

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	160766	1			T7	1		T9	1		T10	4
auto[0]	auto[0]	auto[0:524287]	auto[1]	420134	1			T13	512		T69	8		T54	256
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	125201	1			T11	170		T14	3470		T15	373
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	251325	1			T41	7		T40	258		T59	257
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	115960	1			T10	2		T13	29		T14	53
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	236543	1			T13	896		T41	2		T40	128
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	121864	1			T11	391		T13	22		T14	763
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	264963	1			T13	5		T40	593		T59	3305
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	92870	1			T11	217		T13	33		T14	20
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	268041	1			T13	512		T69	248		T41	1
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	142961	1			T11	14		T13	33		T14	392
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	274684	1			T41	516		T40	1		T44	2033
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	138974	1			T11	3		T14	1388		T15	896
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	239610	1			T41	258		T40	3716		T44	128
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	104314	1			T11	58		T14	3315		T15	60
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	278705	1			T41	9		T40	1433		T44	256
auto[0]	auto[1]	auto[0:524287]	auto[0]	778	1			T56	1		T44	1		T23	4
auto[0]	auto[1]	auto[0:524287]	auto[1]	78093	1			T44	512		T23	385		T63	256
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	4327	1			T10	956		T44	1		T48	4
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	61859	1			T48	2930		T88	256		T23	670
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	886	1			T10	6		T41	1		T40	4
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	69880	1			T23	3934		T49	2083		T104	128
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	2391	1			T41	1		T23	2		T49	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	57218	1			T41	4		T23	513		T104	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	905	1			T13	2		T44	1		T23	7
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	64516	1			T23	646		T104	768		T35	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	563	1			T13	4		T23	3		T49	3
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	63644	1			T23	1		T49	1		T104	3166
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	644	1			T13	4		T41	2		T40	10
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	58301	1			T13	512		T41	5		T40	2
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	2970	1			T10	923		T41	3		T44	3
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	54236	1			T41	9		T44	2822		T23	514
auto[1]	auto[0]	auto[0:524287]	auto[0]	530	1			T13	26		T41	2		T40	14
auto[1]	auto[0]	auto[0:524287]	auto[1]	2498	1			T41	46		T40	14		T44	8
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	388	1			T41	3		T40	16		T59	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	3511	1			T41	5		T59	5		T44	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	435	1			T13	8		T41	2		T51	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2282	1			T41	39		T51	26		T23	10
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	486	1			T40	8		T89	3		T49	3
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	3005	1			T49	32		T104	2		T96	34
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	385	1			T41	1		T40	8		T49	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2761	1			T41	1		T49	13		T197	44
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	463	1			T41	4		T40	13		T44	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1988	1			T41	96		T40	17		T23	6
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	429	1			T41	2		T40	11		T51	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2530	1			T41	20		T51	4		T23	14
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	470	1			T40	23		T51	2		T23	3
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2210	1			T51	5		T23	7		T96	29
auto[1]	auto[1]	auto[0:524287]	auto[0]	76	1			T23	1		T58	3		T96	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	571	1			T96	11		T32	44		T64	68
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	63	1			T97	1		T196	2		T80	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	283	1			T97	14		T196	19		T80	19
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	123	1			T40	3		T23	1		T32	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	597	1			T23	8		T32	21		T97	73
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	98	1			T23	1		T104	1		T32	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	761	1			T23	10		T104	29		T32	6
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	86	1			T23	3		T35	1		T98	12
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	233	1			T23	25		T35	2		T228	34
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	108	1			T49	1		T104	2		T58	5
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	849	1			T49	8		T104	36		T96	10
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	104	1			T89	3		T104	2		T32	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	702	1			T104	32		T32	40		T35	13
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	84	1			T41	1		T23	2		T89	3
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	479	1			T41	22		T23	1		T32	4

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2263106	1			T7	1		T9	1		T10	5
auto[0]	auto[0]	auto[1]	973809	1			T10	1		T11	893		T14	10219
auto[0]	auto[1]	auto[0]	512500	1			T10	6		T13	522		T56	1
auto[0]	auto[1]	auto[1]	8711	1			T10	1879		T49	1		T104	4
auto[1]	auto[0]	auto[0]	23775	1			T13	34		T41	221		T40	114
auto[1]	auto[0]	auto[1]	596	1			T40	10		T59	1		T23	1
auto[1]	auto[1]	auto[0]	5107	1			T41	23		T40	2		T23	52
auto[1]	auto[1]	auto[1]	110	1			T40	1		T89	2		T49	1