Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	3021651	1			T1	1		T3	1		T4	1
all_pins[1]	3021651	1			T1	1		T3	1		T4	1
all_pins[2]	3021651	1			T1	1		T3	1		T4	1
all_pins[3]	3021651	1			T1	1		T3	1		T4	1
all_pins[4]	3021651	1			T1	1		T3	1		T4	1
all_pins[5]	3021651	1			T1	1		T3	1		T4	1
all_pins[6]	3021651	1			T1	1		T3	1		T4	1
all_pins[7]	3021651	1			T1	1		T3	1		T4	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	24146017	1			T1	8		T3	8		T4	8
values[0x1]	27191	1			T32	24		T33	7		T34	103
transitions[0x0=>0x1]	26777	1			T32	21		T33	4		T34	85
transitions[0x1=>0x0]	26789	1			T32	21		T33	4		T34	85

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	3021163	1			T1	1		T3	1		T4	1
all_pins[0]	values[0x1]	488	1			T32	1		T33	1		T34	5
all_pins[0]	transitions[0x0=>0x1]	447	1			T32	1		T34	3		T35	1
all_pins[0]	transitions[0x1=>0x0]	216	1			T32	5		T34	69		T85	6
all_pins[1]	values[0x0]	3021394	1			T1	1		T3	1		T4	1
all_pins[1]	values[0x1]	257	1			T32	5		T33	1		T34	71
all_pins[1]	transitions[0x0=>0x1]	198	1			T32	3		T34	58		T35	2
all_pins[1]	transitions[0x1=>0x0]	155	1			T32	2		T34	2		T85	3
all_pins[2]	values[0x0]	3021437	1			T1	1		T3	1		T4	1
all_pins[2]	values[0x1]	214	1			T32	4		T33	1		T34	15
all_pins[2]	transitions[0x0=>0x1]	167	1			T32	4		T33	1		T34	15
all_pins[2]	transitions[0x1=>0x0]	139	1			T32	2		T34	4		T85	2
all_pins[3]	values[0x0]	3021465	1			T1	1		T3	1		T4	1
all_pins[3]	values[0x1]	186	1			T32	2		T34	4		T85	2
all_pins[3]	transitions[0x0=>0x1]	147	1			T32	2		T34	3		T85	2
all_pins[3]	transitions[0x1=>0x0]	164	1			T32	5		T33	2		T34	2
all_pins[4]	values[0x0]	3021448	1			T1	1		T3	1		T4	1
all_pins[4]	values[0x1]	203	1			T32	5		T33	2		T34	3
all_pins[4]	transitions[0x0=>0x1]	171	1			T32	5		T33	2		T34	3
all_pins[4]	transitions[0x1=>0x0]	187	1			T32	2		T33	1		T34	1
all_pins[5]	values[0x0]	3021432	1			T1	1		T3	1		T4	1
all_pins[5]	values[0x1]	219	1			T32	2		T33	1		T34	1
all_pins[5]	transitions[0x0=>0x1]	130	1			T32	1		T33	1		T34	1
all_pins[5]	transitions[0x1=>0x0]	25338	1			T32	3		T34	2		T85	3
all_pins[6]	values[0x0]	2996224	1			T1	1		T3	1		T4	1
all_pins[6]	values[0x1]	25427	1			T32	4		T34	2		T85	3
all_pins[6]	transitions[0x0=>0x1]	25377	1			T32	4		T34	1		T85	2
all_pins[6]	transitions[0x1=>0x0]	147	1			T32	1		T33	1		T34	1
all_pins[7]	values[0x0]	3021454	1			T1	1		T3	1		T4	1
all_pins[7]	values[0x1]	197	1			T32	1		T33	1		T34	2
all_pins[7]	transitions[0x0=>0x1]	140	1			T32	1		T34	1		T35	1
all_pins[7]	transitions[0x1=>0x0]	443	1			T32	1		T34	4		T35	1