Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19957

1

T7

6

T10

8

T11

6

auto[1]

14888

1

T9

16

T19

14

T55

12

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4873	1			T9	16		T18	12		T19	14
values[1]	3779	1			T7	6		T14	10		T41	27
values[2]	4492	1			T53	16		T41	145		T110	6
values[3]	4007	1			T11	6		T60	8		T226	10
values[4]	4485	1			T10	8		T215	2		T106	8
values[5]	4497	1			T69	2		T56	6		T119	2
values[6]	4840	1			T54	10		T270	2		T65	2
values[7]	3872	1			T55	12		T41	43		T44	26

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4516	1			T56	6		T54	10		T41	27
values[1]	3630	1			T11	6		T53	16		T57	6
values[2]	4571	1			T9	16		T215	2		T107	6
values[3]	4526	1			T65	2		T119	2		T44	23
values[4]	4425	1			T55	12		T244	18		T48	20
values[5]	4570	1			T7	6		T10	8		T14	10
values[6]	4140	1			T69	2		T270	2		T44	46
values[7]	4467	1			T18	12		T19	14		T41	208

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	554	1			T266	10		T32	11		T271	4
auto[0]	values[0]	values[1]	343	1			T66	6		T243	6		T99	100
auto[0]	values[0]	values[2]	244	1			T254	11		T192	8		T272	22
auto[0]	values[0]	values[3]	625	1			T32	10		T225	12		T229	142
auto[0]	values[0]	values[4]	214	1			T242	14		T37	12		T155	12
auto[0]	values[0]	values[5]	286	1			T211	6		T273	14		T264	14
auto[0]	values[0]	values[6]	296	1			T196	15		T274	2		T99	9
auto[0]	values[0]	values[7]	381	1			T18	12		T275	28		T32	12
auto[0]	values[1]	values[0]	273	1			T41	19		T63	16		T32	58
auto[0]	values[1]	values[1]	165	1			T193	30		T149	4		T252	12
auto[0]	values[1]	values[2]	168	1			T196	14		T228	12		T225	12
auto[0]	values[1]	values[3]	261	1			T44	9		T195	6		T192	16
auto[0]	values[1]	values[4]	237	1			T276	16		T85	13		T250	11
auto[0]	values[1]	values[5]	249	1			T7	6		T14	10		T37	11
auto[0]	values[1]	values[6]	303	1			T254	11		T195	14		T37	13
auto[0]	values[1]	values[7]	416	1			T49	9		T238	6		T192	10
auto[0]	values[2]	values[0]	297	1			T110	6		T245	17		T254	13
auto[0]	values[2]	values[1]	312	1			T53	16		T61	111		T193	8
auto[0]	values[2]	values[2]	305	1			T49	48		T32	9		T196	11
auto[0]	values[2]	values[3]	513	1			T268	8		T245	19		T277	2
auto[0]	values[2]	values[4]	446	1			T278	12		T193	23		T225	13
auto[0]	values[2]	values[5]	158	1			T219	20		T196	14		T262	28
auto[0]	values[2]	values[6]	314	1			T64	10		T195	16		T196	66
auto[0]	values[2]	values[7]	273	1			T41	7		T279	4		T246	11
auto[0]	values[3]	values[0]	230	1			T212	2		T194	18		T228	16
auto[0]	values[3]	values[1]	197	1			T11	6		T32	15		T188	10
auto[0]	values[3]	values[2]	266	1			T60	8		T269	8		T58	12
auto[0]	values[3]	values[3]	262	1			T226	10		T198	4		T64	8
auto[0]	values[3]	values[4]	233	1			T280	2		T71	13		T281	13
auto[0]	values[3]	values[5]	287	1			T50	18		T195	11		T193	73
auto[0]	values[3]	values[6]	352	1			T282	12		T195	11		T37	27
auto[0]	values[3]	values[7]	421	1			T283	6		T257	12		T155	10
auto[0]	values[4]	values[0]	452	1			T58	21		T192	11		T284	2
auto[0]	values[4]	values[1]	328	1			T285	2		T286	20		T287	4
auto[0]	values[4]	values[2]	289	1			T215	2		T44	10		T32	14
auto[0]	values[4]	values[3]	191	1			T49	13		T64	9		T228	18
auto[0]	values[4]	values[4]	294	1			T63	12		T58	13		T237	10
auto[0]	values[4]	values[5]	447	1			T10	8		T195	39		T82	11
auto[0]	values[4]	values[6]	296	1			T63	14		T49	26		T192	14
auto[0]	values[4]	values[7]	353	1			T106	8		T264	23		T186	8
auto[0]	values[5]	values[0]	372	1			T56	6		T44	15		T263	6
auto[0]	values[5]	values[1]	133	1			T288	13		T289	10		T290	8
auto[0]	values[5]	values[2]	430	1			T120	8		T258	24		T195	10
auto[0]	values[5]	values[3]	292	1			T119	2		T188	9		T195	20
auto[0]	values[5]	values[4]	146	1			T48	10		T191	8		T64	17
auto[0]	values[5]	values[5]	402	1			T59	15		T58	11		T32	34
auto[0]	values[5]	values[6]	266	1			T69	2		T216	16		T48	12
auto[0]	values[5]	values[7]	404	1			T63	15		T291	2		T99	10
auto[0]	values[6]	values[0]	279	1			T54	10		T34	9		T195	11
auto[0]	values[6]	values[1]	230	1			T57	6		T41	12		T58	12
auto[0]	values[6]	values[2]	635	1			T32	12		T192	12		T292	2
auto[0]	values[6]	values[3]	182	1			T65	2		T246	13		T224	12
auto[0]	values[6]	values[4]	400	1			T244	18		T185	2		T228	15
auto[0]	values[6]	values[5]	461	1			T41	51		T58	13		T32	12
auto[0]	values[6]	values[6]	322	1			T270	2		T44	15		T32	10
auto[0]	values[6]	values[7]	220	1			T41	14		T44	12		T58	6
auto[0]	values[7]	values[0]	242	1			T32	58		T37	12		T293	10
auto[0]	values[7]	values[1]	264	1			T155	42		T294	6		T99	20
auto[0]	values[7]	values[2]	342	1			T58	12		T295	6		T296	26
auto[0]	values[7]	values[3]	381	1			T251	20		T34	9		T195	10
auto[0]	values[7]	values[4]	273	1			T63	9		T32	11		T34	29
auto[0]	values[7]	values[5]	377	1			T220	6		T64	84		T192	11
auto[0]	values[7]	values[6]	205	1			T44	22		T288	10		T297	11
auto[0]	values[7]	values[7]	168	1			T41	12		T49	9		T192	11
auto[1]	values[0]	values[0]	230	1			T32	38		T195	10		T193	6
auto[1]	values[0]	values[1]	254	1			T99	9		T71	6		T218	22
auto[1]	values[0]	values[2]	275	1			T9	16		T254	9		T192	12
auto[1]	values[0]	values[3]	254	1			T32	10		T225	28		T229	2
auto[1]	values[0]	values[4]	320	1			T37	26		T155	8		T281	11
auto[1]	values[0]	values[5]	170	1			T264	7		T64	39		T193	7
auto[1]	values[0]	values[6]	145	1			T196	8		T99	11		T178	8
auto[1]	values[0]	values[7]	282	1			T19	14		T32	52		T298	24
auto[1]	values[1]	values[0]	142	1			T41	8		T63	4		T32	8
auto[1]	values[1]	values[1]	207	1			T193	14		T252	8		T178	35
auto[1]	values[1]	values[2]	210	1			T107	6		T196	6		T228	93
auto[1]	values[1]	values[3]	247	1			T44	14		T195	25		T192	4
auto[1]	values[1]	values[4]	289	1			T62	12		T85	65		T250	9
auto[1]	values[1]	values[5]	250	1			T37	14		T225	8		T260	10
auto[1]	values[1]	values[6]	175	1			T254	9		T195	6		T37	7
auto[1]	values[1]	values[7]	187	1			T49	11		T192	10		T193	4
auto[1]	values[2]	values[0]	213	1			T245	14		T299	4		T254	7
auto[1]	values[2]	values[1]	192	1			T193	12		T99	10		T300	14
auto[1]	values[2]	values[2]	134	1			T49	16		T32	11		T196	9
auto[1]	values[2]	values[3]	257	1			T245	11		T64	7		T301	6
auto[1]	values[2]	values[4]	298	1			T193	17		T225	7		T218	40
auto[1]	values[2]	values[5]	157	1			T196	6		T262	12		T302	22
auto[1]	values[2]	values[6]	336	1			T64	35		T195	4		T196	4
auto[1]	values[2]	values[7]	287	1			T41	138		T303	6		T246	13
auto[1]	values[3]	values[0]	149	1			T228	50		T281	16		T233	3
auto[1]	values[3]	values[1]	207	1			T32	42		T188	17		T34	10
auto[1]	values[3]	values[2]	296	1			T58	8		T196	31		T99	74
auto[1]	values[3]	values[3]	260	1			T64	12		T85	9		T228	8
auto[1]	values[3]	values[4]	244	1			T71	10		T281	7		T297	6
auto[1]	values[3]	values[5]	230	1			T195	105		T193	10		T179	12
auto[1]	values[3]	values[6]	193	1			T195	9		T37	15		T231	20
auto[1]	values[3]	values[7]	180	1			T155	10		T304	18		T281	13
auto[1]	values[4]	values[0]	277	1			T58	19		T192	9		T155	11
auto[1]	values[4]	values[1]	181	1			T246	8		T247	11		T72	7
auto[1]	values[4]	values[2]	202	1			T44	12		T32	6		T34	8
auto[1]	values[4]	values[3]	167	1			T49	16		T253	12		T64	11
auto[1]	values[4]	values[4]	239	1			T63	18		T58	7		T228	7
auto[1]	values[4]	values[5]	327	1			T195	12		T82	9		T85	10
auto[1]	values[4]	values[6]	158	1			T63	6		T49	9		T192	6
auto[1]	values[4]	values[7]	284	1			T264	2		T190	12		T99	8
auto[1]	values[5]	values[0]	253	1			T44	5		T196	23		T305	6
auto[1]	values[5]	values[1]	149	1			T288	7		T289	35		T290	12
auto[1]	values[5]	values[2]	312	1			T195	34		T193	32		T37	5
auto[1]	values[5]	values[3]	257	1			T188	11		T195	6		T37	7
auto[1]	values[5]	values[4]	202	1			T48	10		T191	15		T64	3
auto[1]	values[5]	values[5]	267	1			T59	11		T58	9		T32	8
auto[1]	values[5]	values[6]	289	1			T48	8		T195	13		T192	13
auto[1]	values[5]	values[7]	323	1			T63	5		T99	10		T71	6
auto[1]	values[6]	values[0]	345	1			T34	24		T195	58		T192	13
auto[1]	values[6]	values[1]	324	1			T41	56		T58	8		T193	13
auto[1]	values[6]	values[2]	324	1			T32	8		T192	8		T255	8
auto[1]	values[6]	values[3]	116	1			T246	7		T224	8		T306	6
auto[1]	values[6]	values[4]	247	1			T228	5		T71	14		T246	12
auto[1]	values[6]	values[5]	319	1			T41	10		T58	7		T32	8
auto[1]	values[6]	values[6]	287	1			T44	5		T32	101		T307	4
auto[1]	values[6]	values[7]	149	1			T41	6		T44	12		T58	14
auto[1]	values[7]	values[0]	208	1			T32	5		T37	37		T246	9
auto[1]	values[7]	values[1]	144	1			T155	10		T99	4		T255	11
auto[1]	values[7]	values[2]	139	1			T58	8		T262	9		T288	11
auto[1]	values[7]	values[3]	261	1			T34	11		T195	10		T228	55
auto[1]	values[7]	values[4]	343	1			T55	12		T63	11		T32	82
auto[1]	values[7]	values[5]	183	1			T64	5		T192	9		T308	17
auto[1]	values[7]	values[6]	203	1			T44	4		T309	22		T288	10
auto[1]	values[7]	values[7]	139	1			T41	31		T49	25		T192	9