Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	485	1			T41	1		T44	1		T63	2
auto[ReadAddrCrossIntoMailbox]	349	1			T41	3		T44	1		T49	2
auto[ReadAddrCrossOutOfMailbox]	385	1			T41	2		T59	1		T44	1
auto[ReadAddrCrossAllMailbox]	268	1			T41	1		T59	1		T44	4
auto[ReadAddrOutsideMailbox]	4069	1			T9	4		T11	6		T14	6

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2749

1

T9

2

T11

3

T14

3

auto[1]

2807

1

T9

2

T11

3

T14

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	900	1			T18	6		T54	2		T41	2
read_ops[0x0b]	901	1			T9	4		T11	2		T14	2
read_ops[0x3b]	888	1			T41	5		T44	7		T244	4
read_ops[0x6b]	952	1			T11	4		T53	2		T54	4
read_ops[0xbb]	897	1			T19	2		T41	4		T44	3
read_ops[0xeb]	1018	1			T14	4		T19	2		T53	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	46	1			T191	1		T32	1		T242	2
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	45	1			T34	1		T254	1		T195	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	32	1			T64	1		T196	1		T310	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	30	1			T41	1		T188	1		T64	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	32	1			T193	1		T155	1		T99	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	32	1			T193	2		T228	1		T308	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T44	1		T191	1		T155	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	26	1			T58	1		T32	1		T188	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	315	1			T18	3		T54	1		T41	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	323	1			T18	3		T54	1		T63	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	36	1			T268	1		T120	1		T32	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	45	1			T268	1		T120	1		T49	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	28	1			T44	1		T195	3		T301	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	30	1			T254	1		T64	1		T37	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	28	1			T44	1		T268	1		T37	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	37	1			T59	1		T63	1		T268	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	21	1			T268	1		T58	1		T228	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T59	1		T268	1		T32	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	354	1			T9	2		T11	1		T14	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	301	1			T9	2		T11	1		T14	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	43	1			T259	1		T311	1		T155	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	40	1			T41	1		T259	1		T195	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	32	1			T41	1		T58	1		T278	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	29	1			T32	2		T278	2		T195	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T37	1		T311	1		T228	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	35	1			T41	1		T58	1		T191	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	23	1			T44	2		T63	1		T278	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T188	1		T278	1		T64	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	303	1			T44	4		T244	2		T63	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	338	1			T41	2		T44	1		T244	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T237	1		T32	1		T193	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	36	1			T44	1		T49	2		T237	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	31	1			T188	1		T192	1		T196	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	33	1			T49	2		T195	1		T193	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T195	1		T255	1		T310	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	40	1			T41	1		T58	1		T228	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T275	1		T254	1		T192	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	22	1			T41	1		T44	1		T275	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	370	1			T11	2		T53	1		T54	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	346	1			T11	2		T53	1		T54	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	35	1			T50	1		T191	1		T195	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	47	1			T63	2		T50	1		T193	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	31	1			T58	1		T191	1		T193	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T32	1		T195	1		T192	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	30	1			T58	1		T32	1		T254	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T37	1		T228	2		T312	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	32	1			T275	3		T308	1		T260	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T245	1		T275	3		T254	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	316	1			T19	1		T44	2		T63	3
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	334	1			T19	1		T41	4		T44	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	45	1			T268	1		T50	2		T58	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T268	1		T50	2		T191	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T41	1		T64	1		T196	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T195	1		T37	1		T252	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	32	1			T58	1		T32	2		T195	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	42	1			T64	1		T85	1		T37	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	27	1			T34	1		T64	1		T37	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T245	1		T195	3		T192	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	362	1			T14	2		T19	1		T53	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	407	1			T14	2		T19	1		T53	1