Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4960	1			T55	12		T41	68		T44	20
values[1]	4287	1			T10	8		T14	10		T18	12
values[2]	4429	1			T56	6		T41	61		T49	20
values[3]	3916	1			T7	6		T11	6		T270	2
values[4]	4420	1			T69	2		T53	16		T215	2
values[5]	4568	1			T66	6		T41	20		T106	8
values[6]	4335	1			T9	16		T54	10		T119	2
values[7]	3930	1			T19	14		T65	2		T41	172

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4162	1			T18	12		T41	20		T106	8
values[1]	4563	1			T270	2		T44	43		T216	16
values[2]	4171	1			T55	12		T57	6		T59	26
values[3]	4657	1			T14	10		T66	6		T41	145
values[4]	3945	1			T215	2		T65	2		T44	22
values[5]	4231	1			T56	6		T41	104		T44	24
values[6]	4158	1			T7	6		T9	16		T10	8
values[7]	4958	1			T19	14		T69	2		T53	16

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33939

1

T7

6

T9

16

T10

8

auto[1]

906

1

T55

2

T41

16

T59

1

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	529	1			T193	81		T225	19		T313	12
auto[0]	values[0]	values[1]	717	1			T44	20		T58	17		T191	22
auto[0]	values[0]	values[2]	629	1			T55	10		T64	141		T195	16
auto[0]	values[0]	values[3]	576	1			T254	18		T193	54		T228	20
auto[0]	values[0]	values[4]	538	1			T228	100		T155	51		T308	22
auto[0]	values[0]	values[5]	675	1			T63	19		T193	61		T311	4
auto[0]	values[0]	values[6]	512	1			T196	55		T314	8		T315	14
auto[0]	values[0]	values[7]	640	1			T41	59		T58	19		T37	58
auto[0]	values[1]	values[0]	535	1			T18	12		T196	68		T37	20
auto[0]	values[1]	values[1]	589	1			T219	20		T58	19		T192	20
auto[0]	values[1]	values[2]	421	1			T57	6		T263	6		T194	18
auto[0]	values[1]	values[3]	480	1			T14	10		T245	30		T34	20
auto[0]	values[1]	values[4]	474	1			T212	2		T273	14		T316	2
auto[0]	values[1]	values[5]	631	1			T198	4		T222	8		T221	18
auto[0]	values[1]	values[6]	586	1			T10	8		T32	63		T37	56
auto[0]	values[1]	values[7]	467	1			T44	20		T251	20		T195	30
auto[0]	values[2]	values[0]	478	1			T237	10		T64	49		T195	41
auto[0]	values[2]	values[1]	627	1			T49	20		T193	19		T196	20
auto[0]	values[2]	values[2]	559	1			T274	2		T99	47		T262	26
auto[0]	values[2]	values[3]	525	1			T220	6		T196	42		T81	4
auto[0]	values[2]	values[4]	400	1			T58	19		T245	30		T32	90
auto[0]	values[2]	values[5]	587	1			T56	6		T41	60		T32	42
auto[0]	values[2]	values[6]	564	1			T58	20		T195	20		T37	22
auto[0]	values[2]	values[7]	571	1			T269	8		T253	12		T32	20
auto[0]	values[3]	values[0]	567	1			T32	56		T34	33		T307	4
auto[0]	values[3]	values[1]	510	1			T270	2		T317	10		T230	16
auto[0]	values[3]	values[2]	312	1			T59	25		T254	20		T225	19
auto[0]	values[3]	values[3]	537	1			T195	68		T242	14		T193	36
auto[0]	values[3]	values[4]	371	1			T44	21		T49	34		T186	8
auto[0]	values[3]	values[5]	659	1			T41	43		T44	22		T257	12
auto[0]	values[3]	values[6]	463	1			T7	6		T11	6		T62	10
auto[0]	values[3]	values[7]	401	1			T32	20		T64	89		T252	19
auto[0]	values[4]	values[0]	447	1			T258	24		T37	49		T318	33
auto[0]	values[4]	values[1]	598	1			T240	6		T291	2		T195	18
auto[0]	values[4]	values[2]	507	1			T49	20		T285	2		T298	24
auto[0]	values[4]	values[3]	586	1			T58	20		T278	12		T238	6
auto[0]	values[4]	values[4]	557	1			T215	2		T58	19		T276	16
auto[0]	values[4]	values[5]	390	1			T211	6		T99	78		T246	21
auto[0]	values[4]	values[6]	448	1			T264	25		T218	28		T246	23
auto[0]	values[4]	values[7]	762	1			T69	2		T53	16		T50	18
auto[0]	values[5]	values[0]	675	1			T41	18		T106	8		T48	19
auto[0]	values[5]	values[1]	315	1			T216	16		T229	61		T319	10
auto[0]	values[5]	values[2]	576	1			T244	18		T63	18		T49	42
auto[0]	values[5]	values[3]	564	1			T66	6		T58	20		T193	36
auto[0]	values[5]	values[4]	533	1			T32	20		T188	27		T155	64
auto[0]	values[5]	values[5]	337	1			T61	111		T49	33		T292	2
auto[0]	values[5]	values[6]	561	1			T34	20		T193	19		T228	20
auto[0]	values[5]	values[7]	912	1			T110	6		T283	6		T155	46
auto[0]	values[6]	values[0]	481	1			T299	4		T196	20		T228	20
auto[0]	values[6]	values[1]	569	1			T49	26		T32	20		T271	4
auto[0]	values[6]	values[2]	641	1			T32	25		T192	18		T320	12
auto[0]	values[6]	values[3]	539	1			T268	8		T32	62		T259	4
auto[0]	values[6]	values[4]	617	1			T32	49		T185	2		T64	37
auto[0]	values[6]	values[5]	279	1			T34	32		T321	2		T322	6
auto[0]	values[6]	values[6]	562	1			T9	16		T54	10		T119	2
auto[0]	values[6]	values[7]	530	1			T44	26		T266	10		T196	53
auto[0]	values[7]	values[0]	336	1			T107	6		T193	20		T228	20
auto[0]	values[7]	values[1]	526	1			T44	22		T264	21		T247	22
auto[0]	values[7]	values[2]	408	1			T60	8		T63	19		T196	49
auto[0]	values[7]	values[3]	725	1			T41	142		T58	20		T275	28
auto[0]	values[7]	values[4]	364	1			T65	2		T193	20		T323	4
auto[0]	values[7]	values[5]	576	1			T120	8		T32	111		T192	20
auto[0]	values[7]	values[6]	339	1			T41	26		T226	10		T324	8
auto[0]	values[7]	values[7]	549	1			T19	14		T48	20		T63	30
auto[1]	values[0]	values[0]	15	1			T193	2		T225	1		T313	2
auto[1]	values[0]	values[1]	18	1			T58	3		T191	1		T195	1
auto[1]	values[0]	values[2]	19	1			T55	2		T64	1		T195	4
auto[1]	values[0]	values[3]	13	1			T254	2		T255	1		T246	3
auto[1]	values[0]	values[4]	14	1			T228	5		T155	1		T325	1
auto[1]	values[0]	values[5]	15	1			T63	1		T193	3		T250	1
auto[1]	values[0]	values[6]	18	1			T196	3		T315	4		T326	2
auto[1]	values[0]	values[7]	32	1			T41	9		T58	1		T37	2
auto[1]	values[1]	values[0]	14	1			T196	2		T281	1		T241	1
auto[1]	values[1]	values[1]	12	1			T58	1		T327	1		T328	1
auto[1]	values[1]	values[2]	7	1			T195	2		T329	1		T330	3
auto[1]	values[1]	values[3]	12	1			T301	2		T331	3		T332	1
auto[1]	values[1]	values[4]	12	1			T64	2		T228	1		T325	2
auto[1]	values[1]	values[5]	18	1			T225	3		T288	3		T236	2
auto[1]	values[1]	values[6]	17	1			T32	1		T37	2		T262	1
auto[1]	values[1]	values[7]	12	1			T195	1		T192	1		T289	4
auto[1]	values[2]	values[0]	24	1			T64	2		T195	3		T333	2
auto[1]	values[2]	values[1]	16	1			T193	1		T82	1		T233	1
auto[1]	values[2]	values[2]	19	1			T99	4		T325	2		T179	1
auto[1]	values[2]	values[3]	15	1			T85	1		T37	1		T334	1
auto[1]	values[2]	values[4]	8	1			T58	1		T245	1		T32	3
auto[1]	values[2]	values[5]	12	1			T41	1		T37	4		T246	1
auto[1]	values[2]	values[6]	16	1			T228	3		T281	3		T233	2
auto[1]	values[2]	values[7]	8	1			T193	1		T71	1		T281	1
auto[1]	values[3]	values[0]	12	1			T32	1		T262	2		T335	1
auto[1]	values[3]	values[1]	5	1			T37	1		T336	1		T337	1
auto[1]	values[3]	values[2]	6	1			T59	1		T225	1		T288	1
auto[1]	values[3]	values[3]	18	1			T195	1		T193	1		T224	2
auto[1]	values[3]	values[4]	13	1			T44	1		T49	1		T338	5
auto[1]	values[3]	values[5]	17	1			T44	2		T339	4		T340	1
auto[1]	values[3]	values[6]	16	1			T62	2		T155	1		T334	1
auto[1]	values[3]	values[7]	9	1			T252	1		T281	3		T241	1
auto[1]	values[4]	values[0]	16	1			T281	2		T302	3		T339	4
auto[1]	values[4]	values[1]	16	1			T195	2		T309	4		T218	1
auto[1]	values[4]	values[2]	14	1			T195	2		T288	2		T341	5
auto[1]	values[4]	values[3]	18	1			T195	1		T71	2		T341	2
auto[1]	values[4]	values[4]	15	1			T58	1		T34	2		T155	1
auto[1]	values[4]	values[5]	13	1			T99	1		T246	3		T342	3
auto[1]	values[4]	values[6]	21	1			T246	1		T334	2		T236	3
auto[1]	values[4]	values[7]	12	1			T328	1		T336	1		T343	1
auto[1]	values[5]	values[0]	14	1			T41	2		T48	1		T85	2
auto[1]	values[5]	values[1]	5	1			T297	2		T344	1		T345	1
auto[1]	values[5]	values[2]	21	1			T63	2		T49	2		T228	6
auto[1]	values[5]	values[3]	15	1			T193	2		T346	1		T72	1
auto[1]	values[5]	values[4]	2	1			T71	2		-	-		-	-
auto[1]	values[5]	values[5]	10	1			T49	1		T334	2		T339	1
auto[1]	values[5]	values[6]	15	1			T193	1		T218	3		T72	1
auto[1]	values[5]	values[7]	13	1			T229	1		T178	1		T233	1
auto[1]	values[6]	values[0]	11	1			T247	2		T178	2		T337	2
auto[1]	values[6]	values[1]	18	1			T49	3		T99	1		T246	1
auto[1]	values[6]	values[2]	17	1			T192	2		T247	1		T347	1
auto[1]	values[6]	values[3]	18	1			T32	1		T289	1		T328	2
auto[1]	values[6]	values[4]	11	1			T64	3		T300	2		T72	1
auto[1]	values[6]	values[5]	4	1			T34	1		T342	1		T249	2
auto[1]	values[6]	values[6]	17	1			T195	3		T246	2		T325	3
auto[1]	values[6]	values[7]	21	1			T196	3		T231	4		T308	1
auto[1]	values[7]	values[0]	8	1			T218	2		T262	1		T347	1
auto[1]	values[7]	values[1]	22	1			T44	1		T247	2		T347	1
auto[1]	values[7]	values[2]	15	1			T63	1		T196	2		T72	1
auto[1]	values[7]	values[3]	16	1			T41	3		T64	1		T262	2
auto[1]	values[7]	values[4]	16	1			T252	2		T71	3		T304	4
auto[1]	values[7]	values[5]	8	1			T301	1		T233	4		T348	1
auto[1]	values[7]	values[6]	3	1			T41	1		T71	2		-	-
auto[1]	values[7]	values[7]	19	1			T179	3		T349	2		T328	1