Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	821	1			T32	14		T33	7		T34	17
all_values[1]	821	1			T32	14		T33	7		T34	17
all_values[2]	821	1			T32	14		T33	7		T34	17
all_values[3]	821	1			T32	14		T33	7		T34	17
all_values[4]	821	1			T32	14		T33	7		T34	17
all_values[5]	821	1			T32	14		T33	7		T34	17
all_values[6]	821	1			T32	14		T33	7		T34	17
all_values[7]	821	1			T32	14		T33	7		T34	17

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3567

1

T32

63

T33

33

T34

74

auto[1]

3001

1

T32

49

T33

23

T34

62

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2621

1

T32

45

T33

20

T34

65

auto[1]

3947

1

T32

67

T33

36

T34

71

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3757

1

T32

65

T33

35

T34

84

auto[1]

2811

1

T32

47

T33

21

T34

52

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	161	1			T32	3		T34	3		T35	1
all_values[0]	auto[0]	auto[0]	auto[1]	73	1			T32	2		T33	1		T34	2
all_values[0]	auto[0]	auto[1]	auto[0]	163	1			T32	1		T33	2		T34	2
all_values[0]	auto[0]	auto[1]	auto[1]	76	1			T33	1		T34	3		T35	1
all_values[0]	auto[1]	auto[0]	auto[1]	170	1			T32	6		T33	1		T34	2
all_values[0]	auto[1]	auto[1]	auto[1]	178	1			T32	2		T33	2		T34	5
all_values[1]	auto[0]	auto[0]	auto[0]	150	1			T32	2		T34	3		T190	2
all_values[1]	auto[0]	auto[0]	auto[1]	91	1			T32	1		T33	3		T34	1
all_values[1]	auto[0]	auto[1]	auto[0]	141	1			T32	3		T34	4		T85	2
all_values[1]	auto[0]	auto[1]	auto[1]	73	1			T32	3		T35	1		T85	2
all_values[1]	auto[1]	auto[0]	auto[1]	212	1			T32	1		T33	3		T34	4
all_values[1]	auto[1]	auto[1]	auto[1]	154	1			T32	4		T33	1		T34	5
all_values[2]	auto[0]	auto[0]	auto[0]	184	1			T32	4		T33	2		T34	6
all_values[2]	auto[0]	auto[0]	auto[1]	82	1			T32	1		T33	2		T34	2
all_values[2]	auto[0]	auto[1]	auto[0]	145	1			T32	1		T33	1		T34	4
all_values[2]	auto[0]	auto[1]	auto[1]	71	1			T32	3		T34	1		T85	1
all_values[2]	auto[1]	auto[0]	auto[1]	185	1			T32	3		T33	1		T34	4
all_values[2]	auto[1]	auto[1]	auto[1]	154	1			T32	2		T33	1		T35	1
all_values[3]	auto[0]	auto[0]	auto[0]	163	1			T32	5		T33	1		T34	4
all_values[3]	auto[0]	auto[0]	auto[1]	89	1			T32	1		T33	1		T35	2
all_values[3]	auto[0]	auto[1]	auto[0]	131	1			T32	2		T33	3		T34	5
all_values[3]	auto[0]	auto[1]	auto[1]	87	1			T32	2		T34	1		T85	2
all_values[3]	auto[1]	auto[0]	auto[1]	207	1			T32	2		T33	2		T34	4
all_values[3]	auto[1]	auto[1]	auto[1]	144	1			T32	2		T34	3		T85	4
all_values[4]	auto[0]	auto[0]	auto[0]	165	1			T34	2		T35	2		T85	3
all_values[4]	auto[0]	auto[0]	auto[1]	77	1			T32	1		T33	1		T34	1
all_values[4]	auto[0]	auto[1]	auto[0]	130	1			T32	3		T33	1		T34	5
all_values[4]	auto[0]	auto[1]	auto[1]	87	1			T32	3		T33	2		T190	3
all_values[4]	auto[1]	auto[0]	auto[1]	203	1			T32	4		T33	1		T34	4
all_values[4]	auto[1]	auto[1]	auto[1]	159	1			T32	3		T33	2		T34	5
all_values[5]	auto[0]	auto[0]	auto[0]	273	1			T32	3		T33	3		T34	7
all_values[5]	auto[0]	auto[1]	auto[0]	192	1			T32	6		T33	1		T34	7
all_values[5]	auto[1]	auto[0]	auto[1]	192	1			T32	3		T33	1		T34	2
all_values[5]	auto[1]	auto[1]	auto[1]	164	1			T32	2		T33	2		T34	1
all_values[6]	auto[0]	auto[0]	auto[0]	164	1			T32	5		T33	3		T34	3
all_values[6]	auto[0]	auto[0]	auto[1]	71	1			T33	1		T34	3		T85	1
all_values[6]	auto[0]	auto[1]	auto[0]	153	1			T33	1		T34	3		T35	1
all_values[6]	auto[0]	auto[1]	auto[1]	81	1			T32	2		T33	1		T34	1
all_values[6]	auto[1]	auto[0]	auto[1]	205	1			T32	3		T33	1		T34	5
all_values[6]	auto[1]	auto[1]	auto[1]	147	1			T32	4		T34	2		T85	1
all_values[7]	auto[0]	auto[0]	auto[0]	169	1			T32	6		T33	2		T34	5
all_values[7]	auto[0]	auto[0]	auto[1]	89	1			T32	1		T33	2		T34	2
all_values[7]	auto[0]	auto[1]	auto[0]	137	1			T32	1		T34	2		T85	5
all_values[7]	auto[0]	auto[1]	auto[1]	89	1			T34	2		T35	2		T85	2
all_values[7]	auto[1]	auto[0]	auto[1]	192	1			T32	6		T33	1		T34	5
all_values[7]	auto[1]	auto[1]	auto[1]	145	1			T33	2		T34	1		T35	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal