Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1779

1

T4

2

T8

8

T25

7

auto[1]

1813

1

T4

1

T6

2

T8

13

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1967

1

T6

1

T31

3

T36

7

auto[1]

1625

1

T4

3

T6

1

T8

21

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2826

1

T4

3

T6

2

T8

21

auto[1]

766

1

T31

3

T36

2

T42

1

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	673	1			T4	1		T8	5		T27	4
valid[1]	733	1			T6	1		T8	2		T25	1
valid[2]	752	1			T4	1		T8	6		T25	3
valid[3]	684	1			T4	1		T6	1		T8	6
valid[4]	750	1			T8	2		T24	1		T25	2

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	126	1			T36	1		T42	1		T44	1
auto[0]	auto[0]	valid[0]	auto[1]	144	1			T4	1		T8	1		T27	3
auto[0]	auto[0]	valid[1]	auto[0]	122	1			T36	1		T44	1		T48	2
auto[0]	auto[0]	valid[1]	auto[1]	171	1			T25	1		T27	3		T29	2
auto[0]	auto[0]	valid[2]	auto[0]	111	1			T44	1		T23	3		T359	1
auto[0]	auto[0]	valid[2]	auto[1]	162	1			T4	1		T8	3		T25	3
auto[0]	auto[0]	valid[3]	auto[0]	108	1			T42	1		T44	1		T23	2
auto[0]	auto[0]	valid[3]	auto[1]	156	1			T8	4		T25	2		T27	5
auto[0]	auto[0]	valid[4]	auto[0]	131	1			T42	1		T44	1		T48	1
auto[0]	auto[0]	valid[4]	auto[1]	166	1			T25	1		T27	2		T30	3
auto[0]	auto[1]	valid[0]	auto[0]	113	1			T44	1		T368	2		T23	1
auto[0]	auto[1]	valid[0]	auto[1]	156	1			T8	4		T27	1		T29	3
auto[0]	auto[1]	valid[1]	auto[0]	118	1			T42	1		T44	1		T368	1
auto[0]	auto[1]	valid[1]	auto[1]	158	1			T6	1		T8	2		T27	1
auto[0]	auto[1]	valid[2]	auto[0]	130	1			T36	2		T48	1		T88	1
auto[0]	auto[1]	valid[2]	auto[1]	187	1			T8	3		T27	7		T29	1
auto[0]	auto[1]	valid[3]	auto[0]	122	1			T6	1		T36	1		T44	1
auto[0]	auto[1]	valid[3]	auto[1]	157	1			T4	1		T8	2		T25	1
auto[0]	auto[1]	valid[4]	auto[0]	120	1			T42	1		T48	2		T368	1
auto[0]	auto[1]	valid[4]	auto[1]	168	1			T8	2		T24	1		T25	1
auto[1]	auto[0]	valid[0]	auto[0]	65	1			T88	1		T23	1		T360	1
auto[1]	auto[0]	valid[1]	auto[0]	85	1			T31	1		T44	1		T34	2
auto[1]	auto[0]	valid[2]	auto[0]	87	1			T31	1		T48	2		T88	1
auto[1]	auto[0]	valid[3]	auto[0]	65	1			T48	1		T23	1		T361	2
auto[1]	auto[0]	valid[4]	auto[0]	80	1			T31	1		T23	2		T370	1
auto[1]	auto[1]	valid[0]	auto[0]	69	1			T44	1		T23	1		T63	1
auto[1]	auto[1]	valid[1]	auto[0]	79	1			T42	1		T44	1		T368	1
auto[1]	auto[1]	valid[2]	auto[0]	75	1			T36	1		T44	1		T88	1
auto[1]	auto[1]	valid[3]	auto[0]	76	1			T36	1		T44	1		T368	1
auto[1]	auto[1]	valid[4]	auto[0]	85	1			T368	1		T23	2		T361	2

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal