Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50209

1

T6

44

T24

85

T26

3

auto[1]

16424

1

T4

3

T6

7

T8

266

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48168

1

T4

3

T6

35

T8

266

auto[1]

18465

1

T6

16

T24

36

T26

2

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	34307	1			T4	3		T6	25		T8	135
others[1]	5605	1			T6	6		T8	17		T24	6
others[2]	5630	1			T6	7		T8	24		T24	10
others[3]	6397	1			T6	3		T8	23		T24	12
interest[1]	3609	1			T6	3		T8	21		T24	5
interest[4]	22368	1			T4	3		T6	17		T8	85
interest[64]	11085	1			T6	7		T8	46		T24	15

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	16308	1			T6	14		T24	29		T31	1
auto[0]	auto[0]	others[1]	2691	1			T6	2		T24	3		T26	1
auto[0]	auto[0]	others[2]	2689	1			T6	3		T24	3		T36	6
auto[0]	auto[0]	others[3]	3069	1			T6	3		T24	6		T36	7
auto[0]	auto[0]	interest[1]	1741	1			T24	3		T31	1		T36	5
auto[0]	auto[0]	interest[4]	10534	1			T6	9		T24	20		T31	1
auto[0]	auto[0]	interest[64]	5246	1			T6	6		T24	5		T31	2
auto[0]	auto[1]	others[0]	8578	1			T4	3		T6	3		T8	135
auto[0]	auto[1]	others[1]	1345	1			T6	2		T8	17		T24	2
auto[0]	auto[1]	others[2]	1347	1			T6	1		T8	24		T24	1
auto[0]	auto[1]	others[3]	1550	1			T8	23		T27	38		T29	14
auto[0]	auto[1]	interest[1]	874	1			T6	1		T8	21		T24	1
auto[0]	auto[1]	interest[4]	5695	1			T4	3		T6	1		T8	85
auto[0]	auto[1]	interest[64]	2730	1			T8	46		T24	4		T27	63
auto[1]	auto[0]	others[0]	9421	1			T6	8		T24	16		T26	2
auto[1]	auto[0]	others[1]	1569	1			T6	2		T24	1		T36	6
auto[1]	auto[0]	others[2]	1594	1			T6	3		T24	6		T31	4
auto[1]	auto[0]	others[3]	1778	1			T24	6		T31	1		T36	5
auto[1]	auto[0]	interest[1]	994	1			T6	2		T24	1		T36	4
auto[1]	auto[0]	interest[4]	6139	1			T6	7		T24	12		T26	2
auto[1]	auto[0]	interest[64]	3109	1			T6	1		T24	6		T31	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal