Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2952856	1			T2	1		T3	1		T4	1
all_values[1]	2952856	1			T2	1		T3	1		T4	1
all_values[2]	2952856	1			T2	1		T3	1		T4	1
all_values[3]	2952856	1			T2	1		T3	1		T4	1
all_values[4]	2952856	1			T2	1		T3	1		T4	1
all_values[5]	2952856	1			T2	1		T3	1		T4	1
all_values[6]	2952856	1			T2	1		T3	1		T4	1
all_values[7]	2952856	1			T2	1		T3	1		T4	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23292807

1

T2

8

T3

8

T4

8

auto[1]

330041

1

T21

77

T32

5310

T33

47

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23593078

1

T2

8

T3

8

T4

8

auto[1]

29770

1

T39

184

T21

62

T43

446

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2907835	1			T2	1		T3	1		T4	1
all_values[0]	auto[0]	auto[1]	13581	1			T39	93		T21	2		T43	201
all_values[0]	auto[1]	auto[0]	30999	1			T21	6		T32	1036		T33	2
all_values[0]	auto[1]	auto[1]	441	1			T21	3		T32	19		T34	3
all_values[1]	auto[0]	auto[0]	2918599	1			T2	1		T3	1		T4	1
all_values[1]	auto[0]	auto[1]	9606	1			T39	89		T21	4		T43	124
all_values[1]	auto[1]	auto[0]	24257	1			T21	5		T32	2		T34	1
all_values[1]	auto[1]	auto[1]	394	1			T21	4		T32	3		T33	2
all_values[2]	auto[0]	auto[0]	2899475	1			T2	1		T3	1		T4	1
all_values[2]	auto[0]	auto[1]	3606	1			T39	2		T21	6		T43	121
all_values[2]	auto[1]	auto[0]	49394	1			T21	6		T32	1054		T33	2
all_values[2]	auto[1]	auto[1]	381	1			T21	3		T32	3		T33	1
all_values[3]	auto[0]	auto[0]	2903504	1			T2	1		T3	1		T4	1
all_values[3]	auto[0]	auto[1]	169	1			T21	1		T32	1		T33	1
all_values[3]	auto[1]	auto[0]	49005	1			T21	9		T32	1053		T33	5
all_values[3]	auto[1]	auto[1]	178	1			T21	6		T32	4		T33	4
all_values[4]	auto[0]	auto[0]	2887471	1			T2	1		T3	1		T4	1
all_values[4]	auto[0]	auto[1]	158	1			T21	2		T32	3		T33	3
all_values[4]	auto[1]	auto[0]	65015	1			T21	8		T32	1052		T33	6
all_values[4]	auto[1]	auto[1]	212	1			T21	5		T32	4		T33	2
all_values[5]	auto[0]	auto[0]	2897151	1			T2	1		T3	1		T4	1
all_values[5]	auto[0]	auto[1]	174	1			T21	5		T32	1		T33	1
all_values[5]	auto[1]	auto[0]	55352	1			T21	2		T32	1057		T33	3
all_values[5]	auto[1]	auto[1]	179	1			T21	4		T32	4		T33	3
all_values[6]	auto[0]	auto[0]	2945539	1			T2	1		T3	1		T4	1
all_values[6]	auto[0]	auto[1]	184	1			T21	5		T32	6		T33	3
all_values[6]	auto[1]	auto[0]	6955	1			T21	5		T32	4		T33	5
all_values[6]	auto[1]	auto[1]	178	1			T21	4		T32	5		T33	4
all_values[7]	auto[0]	auto[0]	2905593	1			T2	1		T3	1		T4	1
all_values[7]	auto[0]	auto[1]	162	1			T21	5		T32	6		T34	4
all_values[7]	auto[1]	auto[0]	46934	1			T21	4		T32	5		T33	7
all_values[7]	auto[1]	auto[1]	167	1			T21	3		T32	5		T33	1