Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.03 98.38 94.01 98.62 89.36 97.19 95.45 99.21


Total tests in report: 1131
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
65.65 65.65 92.43 92.43 80.91 80.91 85.24 85.24 26.67 26.67 89.23 89.23 71.83 71.83 13.27 13.27 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_mailbox.1080944016
78.10 12.45 95.73 3.31 88.45 7.54 85.73 0.49 66.67 40.00 93.59 4.36 81.37 9.53 35.20 21.93 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_and_tpm.3444592950
82.37 4.26 96.08 0.34 88.93 0.49 85.73 0.00 84.44 17.78 94.08 0.49 81.37 0.00 45.94 10.74 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_and_tpm.3264599360
85.29 2.92 97.31 1.24 90.71 1.78 88.48 2.76 88.89 4.44 95.94 1.86 84.35 2.99 51.34 5.40 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_all.820942708
87.80 2.51 97.76 0.45 91.75 1.04 89.67 1.18 88.89 0.00 96.50 0.56 84.50 0.14 65.54 14.21 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_stress_all.270870617
89.43 1.62 97.76 0.00 91.94 0.19 90.45 0.79 88.89 0.00 96.53 0.03 93.17 8.68 67.23 1.68 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1670611944
90.79 1.36 97.84 0.08 92.05 0.11 90.75 0.30 88.89 0.00 96.64 0.10 93.31 0.14 76.04 8.81 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_stress_all.2344339533
91.50 0.72 98.01 0.17 92.05 0.00 95.47 4.72 88.89 0.00 96.75 0.12 93.31 0.00 76.04 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_ram_cfg.2258276597
92.14 0.64 98.01 0.00 92.08 0.02 96.26 0.79 88.89 0.00 96.75 0.00 93.31 0.00 79.70 3.66 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_stress_all.2861790700
92.69 0.54 98.11 0.10 92.21 0.14 96.26 0.00 91.11 2.22 96.85 0.10 93.46 0.14 80.79 1.09 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_read_hw_reg.3116794770
93.18 0.50 98.21 0.09 92.36 0.15 96.65 0.39 93.33 2.22 96.94 0.08 93.46 0.00 81.34 0.54 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_upload.2170834807
93.68 0.49 98.21 0.00 92.36 0.00 96.65 0.00 93.33 0.00 96.94 0.00 93.60 0.14 84.65 3.32 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_stress_all.45820823
94.06 0.38 98.21 0.00 92.38 0.01 96.65 0.00 93.33 0.00 96.94 0.00 93.60 0.00 87.28 2.62 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_and_tpm_min_idle.676298046
94.37 0.32 98.22 0.01 92.41 0.04 98.43 1.77 93.33 0.00 96.96 0.02 93.74 0.14 87.52 0.25 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_sec_cm.961758637
94.63 0.26 98.34 0.12 92.97 0.56 98.43 0.00 93.33 0.00 97.13 0.17 94.31 0.57 87.92 0.40 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_mode.1626650161
94.84 0.21 98.34 0.00 92.97 0.00 98.43 0.00 93.33 0.00 97.13 0.00 94.31 0.00 89.41 1.49 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_and_tpm_min_idle.1482040552
95.03 0.18 98.34 0.00 92.97 0.00 98.43 0.00 93.33 0.00 97.13 0.00 94.31 0.00 90.69 1.29 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_and_tpm_min_idle.71002351
95.18 0.16 98.34 0.00 92.97 0.00 98.43 0.00 93.33 0.00 97.13 0.00 94.31 0.00 91.78 1.09 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_all.2170501522
95.33 0.15 98.35 0.01 93.01 0.04 98.43 0.00 93.33 0.00 97.14 0.02 94.31 0.00 92.77 0.99 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_intg_err.968355493
95.48 0.14 98.35 0.00 93.81 0.80 98.43 0.00 93.33 0.00 97.14 0.00 94.31 0.00 92.97 0.20 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_errors.3649176398
95.60 0.13 98.35 0.00 93.81 0.00 98.43 0.00 93.33 0.00 97.14 0.00 94.31 0.00 93.86 0.89 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_all.1032877458
95.73 0.12 98.35 0.00 93.82 0.01 98.43 0.00 93.33 0.00 97.14 0.00 95.16 0.85 93.86 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1366783330
95.85 0.12 98.35 0.00 93.82 0.00 98.43 0.00 93.33 0.00 97.14 0.00 95.16 0.00 94.70 0.84 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_stress_all.3009697408
95.94 0.09 98.35 0.00 93.82 0.00 98.43 0.00 93.33 0.00 97.14 0.00 95.31 0.14 95.20 0.50 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_stress_all.3430759326
96.02 0.08 98.35 0.00 93.83 0.01 98.43 0.00 93.33 0.00 97.14 0.00 95.31 0.00 95.74 0.54 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_mode_ignore_cmds.3728531606
96.09 0.07 98.35 0.00 93.83 0.00 98.43 0.00 93.33 0.00 97.14 0.00 95.31 0.00 96.24 0.50 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_and_tpm.467303917
96.15 0.06 98.35 0.00 93.83 0.00 98.43 0.00 93.33 0.00 97.14 0.00 95.31 0.00 96.63 0.40 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_stress_all.4125532269
96.20 0.06 98.35 0.00 93.83 0.00 98.43 0.00 93.33 0.00 97.14 0.00 95.31 0.00 97.03 0.40 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_stress_all.415554134
96.24 0.04 98.35 0.00 93.83 0.00 98.43 0.00 93.33 0.00 97.14 0.00 95.31 0.00 97.33 0.30 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_all.1347240943
96.28 0.04 98.37 0.03 93.87 0.04 98.62 0.20 93.33 0.00 97.14 0.00 95.31 0.00 97.33 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_alert_test.2081029517
96.32 0.04 98.37 0.00 93.87 0.00 98.62 0.00 93.33 0.00 97.14 0.00 95.31 0.00 97.57 0.25 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_mode_ignore_cmds.3557089056
96.35 0.04 98.37 0.00 93.87 0.00 98.62 0.00 93.33 0.00 97.14 0.00 95.31 0.00 97.82 0.25 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_stress_all.2632456032
96.38 0.03 98.37 0.00 93.87 0.00 98.62 0.00 93.33 0.00 97.14 0.00 95.31 0.00 98.02 0.20 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_and_tpm.3527367058
96.40 0.02 98.38 0.01 93.87 0.00 98.62 0.00 93.33 0.00 97.16 0.02 95.45 0.14 98.02 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_pass_addr_payload_swap.767834035
96.43 0.02 98.38 0.00 93.87 0.00 98.62 0.00 93.33 0.00 97.16 0.00 95.45 0.00 98.17 0.15 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_mode.1857093412
96.45 0.02 98.38 0.00 93.87 0.00 98.62 0.00 93.33 0.00 97.16 0.00 95.45 0.00 98.32 0.15 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_and_tpm_min_idle.1183246970
96.47 0.02 98.38 0.00 93.92 0.05 98.62 0.00 93.33 0.00 97.19 0.03 95.45 0.00 98.37 0.05 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_mode_ignore_cmds.3142822720
96.48 0.02 98.38 0.00 93.93 0.01 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 98.47 0.10 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_intg_err.406616096
96.50 0.01 98.38 0.00 93.98 0.05 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 98.51 0.05 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.2266862507
96.51 0.01 98.38 0.00 93.98 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 98.61 0.10 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_all.1684139287
96.52 0.01 98.38 0.00 93.98 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 98.71 0.10 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_all.182354395
96.54 0.01 98.38 0.00 93.98 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 98.81 0.10 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_and_tpm.2464367904
96.55 0.01 98.38 0.00 93.98 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 98.91 0.10 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_mode_ignore_cmds.1918208228
96.56 0.01 98.38 0.00 93.98 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 98.96 0.05 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.3707591982
96.57 0.01 98.38 0.00 93.98 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 99.01 0.05 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_intg_err.2509458250
96.57 0.01 98.38 0.00 93.98 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 99.06 0.05 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_mode.354701999
96.58 0.01 98.38 0.00 93.98 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 99.11 0.05 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_stress_all.2070725678
96.59 0.01 98.38 0.00 93.98 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 99.16 0.05 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_all.1952773075
96.60 0.01 98.38 0.00 93.98 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 99.21 0.05 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_all.2216530823
96.60 0.01 98.38 0.00 93.99 0.01 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 99.21 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1093995853
96.60 0.01 98.38 0.00 94.01 0.01 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 99.21 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.80234743

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.442222202
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.4267070463
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2366255574
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.4101736030
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.3387214708
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.2968639232
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.1447154102
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.128828067
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.1701869509
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.4069846706
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.709714582
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.80221880
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.2640152156
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.1425933976
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.565848735
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2832794319
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.1792523389
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.653389675
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_rw.2085255284
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_intr_test.2461354002
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2179822089
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_errors.354050504
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_intg_err.3103609991
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.370332207
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_rw.1727412703
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_intr_test.74950804
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.4107954002
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_errors.1923268450
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_intg_err.216237540
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3614896791
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_rw.499791133
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_intr_test.3722933665
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1098139249
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_errors.253459234
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_intg_err.755677692
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.680314767
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_rw.3942969540
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_intr_test.1126156313
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1071545893
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/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_alert_test.3965420320
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_cfg_cmd.648613314
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_csb_read.1033172369
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_and_tpm.233003516
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_and_tpm_min_idle.1665541657
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_mode.368915052
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_mode_ignore_cmds.2149321593
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_intercept.1385419617
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_mailbox.3475016242
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.613581095
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/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_alert_test.726234818
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/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_csb_read.3907122352
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/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_and_tpm.3808668680
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_and_tpm_min_idle.3054276200
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_mode.3353480208
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/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_and_tpm_min_idle.2987511109
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_mode.3828115998
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_mode_ignore_cmds.429385428
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_intercept.3772231556
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_mailbox.708717975
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.1179300718
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.3534223541
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.514337421
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_all.3577147041
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.2735496041
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_rw.3345415740
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.4107021351
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_upload.3455373037



Total test records in report: 1131
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_sec_cm.3363901607 Aug 29 03:03:04 AM UTC 24 Aug 29 03:03:07 AM UTC 24 200627320 ps
T2 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_csb_read.1671741135 Aug 29 03:00:27 AM UTC 24 Aug 29 03:00:29 AM UTC 24 105088494 ps
T3 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_ram_cfg.2258276597 Aug 29 03:00:27 AM UTC 24 Aug 29 03:00:29 AM UTC 24 27413910 ps
T4 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_sts_read.2290535576 Aug 29 03:00:28 AM UTC 24 Aug 29 03:00:30 AM UTC 24 49379870 ps
T5 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_rw.3505878792 Aug 29 03:00:28 AM UTC 24 Aug 29 03:00:31 AM UTC 24 92366199 ps
T6 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_cfg_cmd.1613668759 Aug 29 03:00:30 AM UTC 24 Aug 29 03:00:36 AM UTC 24 212250520 ps
T7 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_pass_addr_payload_swap.2638582693 Aug 29 03:00:29 AM UTC 24 Aug 29 03:00:38 AM UTC 24 1199780398 ps
T8 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_intercept.748824408 Aug 29 03:00:29 AM UTC 24 Aug 29 03:00:39 AM UTC 24 345755491 ps
T9 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_mailbox.1080944016 Aug 29 03:00:29 AM UTC 24 Aug 29 03:00:43 AM UTC 24 756444872 ps
T10 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_sec_cm.961758637 Aug 29 03:00:43 AM UTC 24 Aug 29 03:00:47 AM UTC 24 294098773 ps
T11 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_read_buffer_direct.3961473063 Aug 29 03:00:33 AM UTC 24 Aug 29 03:00:48 AM UTC 24 1691336021 ps
T23 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_alert_test.2081029517 Aug 29 03:00:47 AM UTC 24 Aug 29 03:00:50 AM UTC 24 13389264 ps
T12 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_upload.2170834807 Aug 29 03:00:30 AM UTC 24 Aug 29 03:00:52 AM UTC 24 1211011776 ps
T13 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_csb_read.1071444428 Aug 29 03:00:50 AM UTC 24 Aug 29 03:00:52 AM UTC 24 32312707 ps
T14 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_mode.1626650161 Aug 29 03:00:30 AM UTC 24 Aug 29 03:00:52 AM UTC 24 5370360379 ps
T15 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_all.820942708 Aug 29 03:00:27 AM UTC 24 Aug 29 03:00:55 AM UTC 24 4439168302 ps
T24 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_sts_read.987442837 Aug 29 03:00:53 AM UTC 24 Aug 29 03:00:56 AM UTC 24 257221004 ps
T25 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_rw.4287335882 Aug 29 03:00:54 AM UTC 24 Aug 29 03:00:59 AM UTC 24 304973617 ps
T16 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_pass_cmd_filtering.405317133 Aug 29 03:00:56 AM UTC 24 Aug 29 03:01:00 AM UTC 24 269243816 ps
T17 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_intercept.3500735864 Aug 29 03:01:00 AM UTC 24 Aug 29 03:01:07 AM UTC 24 193756063 ps
T18 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_pass_cmd_filtering.1560133758 Aug 29 03:00:28 AM UTC 24 Aug 29 03:01:07 AM UTC 24 91999624141 ps
T26 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_read_hw_reg.3914885435 Aug 29 03:00:53 AM UTC 24 Aug 29 03:01:07 AM UTC 24 12801484187 ps
T27 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_all.2391017234 Aug 29 03:00:53 AM UTC 24 Aug 29 03:01:12 AM UTC 24 2432219762 ps
T102 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_cfg_cmd.211052988 Aug 29 03:01:07 AM UTC 24 Aug 29 03:01:13 AM UTC 24 207621585 ps
T42 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_mode.829413085 Aug 29 03:01:08 AM UTC 24 Aug 29 03:01:16 AM UTC 24 858253691 ps
T28 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_read_hw_reg.3116794770 Aug 29 03:00:27 AM UTC 24 Aug 29 03:01:17 AM UTC 24 36419868306 ps
T41 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_read_buffer_direct.1748029876 Aug 29 03:01:13 AM UTC 24 Aug 29 03:01:25 AM UTC 24 2258095325 ps
T48 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_mailbox.2782930033 Aug 29 03:01:01 AM UTC 24 Aug 29 03:01:28 AM UTC 24 1347282883 ps
T47 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_pass_addr_payload_swap.767834035 Aug 29 03:00:56 AM UTC 24 Aug 29 03:01:30 AM UTC 24 17671986051 ps
T19 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_sec_cm.1888201802 Aug 29 03:01:30 AM UTC 24 Aug 29 03:01:33 AM UTC 24 148380628 ps
T90 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_alert_test.2314059802 Aug 29 03:01:30 AM UTC 24 Aug 29 03:01:33 AM UTC 24 33284305 ps
T89 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_csb_read.2108699885 Aug 29 03:01:31 AM UTC 24 Aug 29 03:01:34 AM UTC 24 36565176 ps
T29 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_sts_read.3473869360 Aug 29 03:01:35 AM UTC 24 Aug 29 03:01:38 AM UTC 24 211900189 ps
T88 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_upload.2368031180 Aug 29 03:01:07 AM UTC 24 Aug 29 03:01:39 AM UTC 24 4449007705 ps
T30 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_rw.3488522894 Aug 29 03:01:36 AM UTC 24 Aug 29 03:01:40 AM UTC 24 104372903 ps
T87 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_pass_cmd_filtering.3628826413 Aug 29 03:01:39 AM UTC 24 Aug 29 03:01:44 AM UTC 24 89739358 ps
T103 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_read_hw_reg.339800184 Aug 29 03:01:33 AM UTC 24 Aug 29 03:01:45 AM UTC 24 8229335001 ps
T50 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_upload.1208137089 Aug 29 03:01:46 AM UTC 24 Aug 29 03:01:51 AM UTC 24 137368362 ps
T37 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_all.215174560 Aug 29 03:01:33 AM UTC 24 Aug 29 03:01:52 AM UTC 24 543245599 ps
T38 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_mode_ignore_cmds.3538480033 Aug 29 03:01:10 AM UTC 24 Aug 29 03:01:55 AM UTC 24 1460542565 ps
T109 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_cfg_cmd.3055006345 Aug 29 03:01:52 AM UTC 24 Aug 29 03:01:56 AM UTC 24 206368603 ps
T361 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_mailbox.3507816474 Aug 29 03:01:45 AM UTC 24 Aug 29 03:01:57 AM UTC 24 826098721 ps
T46 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_mode.3820352872 Aug 29 03:01:53 AM UTC 24 Aug 29 03:02:00 AM UTC 24 522667360 ps
T51 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_intercept.3414311120 Aug 29 03:01:41 AM UTC 24 Aug 29 03:02:03 AM UTC 24 24131922540 ps
T45 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_mode_ignore_cmds.2810810291 Aug 29 03:01:56 AM UTC 24 Aug 29 03:02:04 AM UTC 24 277049574 ps
T86 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_read_buffer_direct.1490087519 Aug 29 03:01:57 AM UTC 24 Aug 29 03:02:06 AM UTC 24 275173997 ps
T20 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_sec_cm.364854843 Aug 29 03:02:07 AM UTC 24 Aug 29 03:02:09 AM UTC 24 178243357 ps
T91 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_alert_test.50396994 Aug 29 03:02:10 AM UTC 24 Aug 29 03:02:12 AM UTC 24 36199643 ps
T116 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_csb_read.1578721097 Aug 29 03:02:13 AM UTC 24 Aug 29 03:02:15 AM UTC 24 137357262 ps
T52 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_pass_addr_payload_swap.3121634673 Aug 29 03:01:40 AM UTC 24 Aug 29 03:02:16 AM UTC 24 21695082600 ps
T106 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_read_hw_reg.692961099 Aug 29 03:02:17 AM UTC 24 Aug 29 03:02:26 AM UTC 24 509728365 ps
T39 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_and_tpm.3444592950 Aug 29 03:00:39 AM UTC 24 Aug 29 03:02:27 AM UTC 24 4028428691 ps
T59 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_sts_read.423271568 Aug 29 03:02:27 AM UTC 24 Aug 29 03:02:30 AM UTC 24 63481161 ps
T40 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_all.1684139287 Aug 29 03:00:37 AM UTC 24 Aug 29 03:02:31 AM UTC 24 23449746870 ps
T60 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_rw.2597384864 Aug 29 03:02:27 AM UTC 24 Aug 29 03:02:32 AM UTC 24 851439565 ps
T61 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_all.3480455341 Aug 29 03:01:57 AM UTC 24 Aug 29 03:02:32 AM UTC 24 1168294070 ps
T115 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_intercept.467109834 Aug 29 03:02:33 AM UTC 24 Aug 29 03:02:37 AM UTC 24 32043407 ps
T62 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_pass_addr_payload_swap.1428388804 Aug 29 03:02:33 AM UTC 24 Aug 29 03:02:37 AM UTC 24 51384378 ps
T63 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_mailbox.860940341 Aug 29 03:02:34 AM UTC 24 Aug 29 03:02:41 AM UTC 24 719380497 ps
T362 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_mode_ignore_cmds.403649112 Aug 29 03:02:42 AM UTC 24 Aug 29 03:02:44 AM UTC 24 34834826 ps
T64 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_all.477676950 Aug 29 03:02:18 AM UTC 24 Aug 29 03:02:47 AM UTC 24 2214954524 ps
T65 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_cfg_cmd.2026570057 Aug 29 03:02:38 AM UTC 24 Aug 29 03:02:48 AM UTC 24 1698241025 ps
T66 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_read_buffer_direct.1841257869 Aug 29 03:02:45 AM UTC 24 Aug 29 03:02:52 AM UTC 24 244495995 ps
T114 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_mode.3637849796 Aug 29 03:02:42 AM UTC 24 Aug 29 03:03:01 AM UTC 24 1225911973 ps
T49 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_and_tpm_min_idle.71002351 Aug 29 03:00:40 AM UTC 24 Aug 29 03:03:02 AM UTC 24 36848355255 ps
T21 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_stress_all.625980114 Aug 29 03:03:02 AM UTC 24 Aug 29 03:03:04 AM UTC 24 134631796 ps
T191 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_upload.1357283185 Aug 29 03:02:38 AM UTC 24 Aug 29 03:03:04 AM UTC 24 10267672457 ps
T363 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_csb_read.1583323740 Aug 29 03:03:05 AM UTC 24 Aug 29 03:03:07 AM UTC 24 44133162 ps
T364 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_alert_test.2554681426 Aug 29 03:03:05 AM UTC 24 Aug 29 03:03:07 AM UTC 24 25327193 ps
T365 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_sts_read.1125914799 Aug 29 03:03:10 AM UTC 24 Aug 29 03:03:13 AM UTC 24 103633334 ps
T67 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_rw.2781969692 Aug 29 03:03:13 AM UTC 24 Aug 29 03:03:16 AM UTC 24 218825498 ps
T117 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_pass_cmd_filtering.4270407123 Aug 29 03:03:16 AM UTC 24 Aug 29 03:03:20 AM UTC 24 116870767 ps
T366 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_read_hw_reg.480392390 Aug 29 03:03:08 AM UTC 24 Aug 29 03:03:22 AM UTC 24 3751374885 ps
T104 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_all.2469055164 Aug 29 03:03:08 AM UTC 24 Aug 29 03:03:22 AM UTC 24 2372891386 ps
T367 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_intercept.757758690 Aug 29 03:03:23 AM UTC 24 Aug 29 03:03:28 AM UTC 24 105115860 ps
T368 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_mailbox.1533270852 Aug 29 03:03:24 AM UTC 24 Aug 29 03:03:28 AM UTC 24 71310951 ps
T53 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_pass_addr_payload_swap.592417840 Aug 29 03:03:21 AM UTC 24 Aug 29 03:03:29 AM UTC 24 723183628 ps
T108 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_pass_cmd_filtering.2343735577 Aug 29 03:02:30 AM UTC 24 Aug 29 03:03:32 AM UTC 24 9493962435 ps
T369 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_upload.414398725 Aug 29 03:03:29 AM UTC 24 Aug 29 03:03:33 AM UTC 24 57150297 ps
T118 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_cfg_cmd.1373486183 Aug 29 03:03:29 AM UTC 24 Aug 29 03:03:34 AM UTC 24 342977674 ps
T160 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_mode.2858825983 Aug 29 03:03:30 AM UTC 24 Aug 29 03:03:39 AM UTC 24 841806301 ps
T43 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_and_tpm_min_idle.676298046 Aug 29 03:01:17 AM UTC 24 Aug 29 03:03:45 AM UTC 24 52838635063 ps
T22 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_sec_cm.3133129894 Aug 29 03:03:49 AM UTC 24 Aug 29 03:03:51 AM UTC 24 146666583 ps
T370 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_alert_test.3803645032 Aug 29 03:03:52 AM UTC 24 Aug 29 03:03:54 AM UTC 24 16355755 ps
T371 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_csb_read.529142286 Aug 29 03:03:55 AM UTC 24 Aug 29 03:03:57 AM UTC 24 59593300 ps
T161 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_read_buffer_direct.2392825104 Aug 29 03:03:34 AM UTC 24 Aug 29 03:04:00 AM UTC 24 4405452367 ps
T84 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_all.3822641142 Aug 29 03:03:35 AM UTC 24 Aug 29 03:04:08 AM UTC 24 3528053422 ps
T372 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_read_hw_reg.3043211204 Aug 29 03:04:01 AM UTC 24 Aug 29 03:04:09 AM UTC 24 636556200 ps
T373 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_sts_read.2690478033 Aug 29 03:04:10 AM UTC 24 Aug 29 03:04:12 AM UTC 24 144483506 ps
T360 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_rw.3921874580 Aug 29 03:04:10 AM UTC 24 Aug 29 03:04:18 AM UTC 24 408929442 ps
T85 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_mode_ignore_cmds.2045828857 Aug 29 03:00:31 AM UTC 24 Aug 29 03:04:19 AM UTC 24 20412176058 ps
T44 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_and_tpm.467303917 Aug 29 03:01:17 AM UTC 24 Aug 29 03:04:20 AM UTC 24 9979077043 ps
T288 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_pass_addr_payload_swap.143972340 Aug 29 03:04:19 AM UTC 24 Aug 29 03:04:28 AM UTC 24 1009335005 ps
T374 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_upload.4088581886 Aug 29 03:04:29 AM UTC 24 Aug 29 03:04:33 AM UTC 24 157993146 ps
T375 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_mode.2727612264 Aug 29 03:04:35 AM UTC 24 Aug 29 03:04:41 AM UTC 24 101676807 ps
T276 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_cfg_cmd.1586486778 Aug 29 03:04:30 AM UTC 24 Aug 29 03:04:47 AM UTC 24 6940588230 ps
T376 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_all.2742045760 Aug 29 03:04:48 AM UTC 24 Aug 29 03:04:50 AM UTC 24 16480634 ps
T105 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_and_tpm.3264599360 Aug 29 03:03:39 AM UTC 24 Aug 29 03:04:51 AM UTC 24 3321705180 ps
T253 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_intercept.4135707023 Aug 29 03:04:20 AM UTC 24 Aug 29 03:04:56 AM UTC 24 5987514896 ps
T162 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_read_buffer_direct.1786294116 Aug 29 03:04:42 AM UTC 24 Aug 29 03:04:57 AM UTC 24 677925013 ps
T377 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_alert_test.3659442210 Aug 29 03:04:57 AM UTC 24 Aug 29 03:04:59 AM UTC 24 46225922 ps
T378 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_csb_read.885098339 Aug 29 03:04:58 AM UTC 24 Aug 29 03:05:00 AM UTC 24 21053643 ps
T272 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_mailbox.2058812592 Aug 29 03:04:21 AM UTC 24 Aug 29 03:05:01 AM UTC 24 1459476495 ps
T354 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_all.1363060266 Aug 29 03:04:01 AM UTC 24 Aug 29 03:05:03 AM UTC 24 7362540611 ps
T379 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_sts_read.4177658634 Aug 29 03:05:03 AM UTC 24 Aug 29 03:05:05 AM UTC 24 172082470 ps
T380 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_read_hw_reg.1323921023 Aug 29 03:05:01 AM UTC 24 Aug 29 03:05:10 AM UTC 24 2221200995 ps
T234 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_pass_cmd_filtering.340331505 Aug 29 03:04:13 AM UTC 24 Aug 29 03:05:11 AM UTC 24 26567084473 ps
T190 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_and_tpm_min_idle.2575194166 Aug 29 03:02:53 AM UTC 24 Aug 29 03:05:12 AM UTC 24 7750357284 ps
T357 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_rw.294980750 Aug 29 03:05:04 AM UTC 24 Aug 29 03:05:14 AM UTC 24 1228062353 ps
T195 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_and_tpm_min_idle.1523746831 Aug 29 03:04:51 AM UTC 24 Aug 29 03:05:15 AM UTC 24 711933496 ps
T238 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_pass_addr_payload_swap.4222674751 Aug 29 03:05:10 AM UTC 24 Aug 29 03:05:15 AM UTC 24 399929021 ps
T54 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_and_tpm.2029215979 Aug 29 03:02:48 AM UTC 24 Aug 29 03:05:22 AM UTC 24 8205946392 ps
T275 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_upload.4195278969 Aug 29 03:05:14 AM UTC 24 Aug 29 03:05:23 AM UTC 24 229332359 ps
T248 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_mode.2674679395 Aug 29 03:05:16 AM UTC 24 Aug 29 03:05:24 AM UTC 24 466024410 ps
T279 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_cfg_cmd.1101003868 Aug 29 03:05:15 AM UTC 24 Aug 29 03:05:26 AM UTC 24 3026086235 ps
T260 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_mode_ignore_cmds.1974107666 Aug 29 03:05:16 AM UTC 24 Aug 29 03:05:29 AM UTC 24 1712873535 ps
T163 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_read_buffer_direct.3395400827 Aug 29 03:05:23 AM UTC 24 Aug 29 03:05:33 AM UTC 24 1064286029 ps
T381 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_alert_test.1306815204 Aug 29 03:05:34 AM UTC 24 Aug 29 03:05:36 AM UTC 24 20024633 ps
T382 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_csb_read.1033172369 Aug 29 03:05:37 AM UTC 24 Aug 29 03:05:40 AM UTC 24 28547012 ps
T31 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_stress_all.2344339533 Aug 29 03:00:42 AM UTC 24 Aug 29 03:05:40 AM UTC 24 47090915240 ps
T356 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_all.3703981275 Aug 29 03:05:02 AM UTC 24 Aug 29 03:05:54 AM UTC 24 11064444998 ps
T32 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_stress_all.2861790700 Aug 29 03:02:05 AM UTC 24 Aug 29 03:05:55 AM UTC 24 78539178357 ps
T383 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_read_hw_reg.3552645591 Aug 29 03:05:42 AM UTC 24 Aug 29 03:05:56 AM UTC 24 3438576997 ps
T384 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_sts_read.664055489 Aug 29 03:05:55 AM UTC 24 Aug 29 03:05:57 AM UTC 24 163740511 ps
T267 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_pass_cmd_filtering.1530732159 Aug 29 03:05:06 AM UTC 24 Aug 29 03:05:59 AM UTC 24 9664835597 ps
T348 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_all.2321680335 Aug 29 03:05:44 AM UTC 24 Aug 29 03:05:59 AM UTC 24 5069052203 ps
T196 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_and_tpm.4280030872 Aug 29 03:04:49 AM UTC 24 Aug 29 03:06:00 AM UTC 24 25548832395 ps
T358 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_rw.2513778667 Aug 29 03:05:56 AM UTC 24 Aug 29 03:06:03 AM UTC 24 727400925 ps
T218 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_upload.308557459 Aug 29 03:06:01 AM UTC 24 Aug 29 03:06:07 AM UTC 24 1340530179 ps
T229 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_pass_cmd_filtering.891446799 Aug 29 03:05:57 AM UTC 24 Aug 29 03:06:10 AM UTC 24 380499087 ps
T281 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_cfg_cmd.648613314 Aug 29 03:06:04 AM UTC 24 Aug 29 03:06:11 AM UTC 24 213363212 ps
T385 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_mailbox.4167408338 Aug 29 03:05:12 AM UTC 24 Aug 29 03:06:12 AM UTC 24 5040444396 ps
T386 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_mode_ignore_cmds.2149321593 Aug 29 03:06:11 AM UTC 24 Aug 29 03:06:13 AM UTC 24 42451555 ps
T55 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_mode_ignore_cmds.3142822720 Aug 29 03:04:40 AM UTC 24 Aug 29 03:06:14 AM UTC 24 8388637921 ps
T95 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_all.735270355 Aug 29 03:01:13 AM UTC 24 Aug 29 03:06:16 AM UTC 24 97603756660 ps
T164 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_mode.368915052 Aug 29 03:06:07 AM UTC 24 Aug 29 03:06:18 AM UTC 24 683476342 ps
T387 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_alert_test.3965420320 Aug 29 03:06:17 AM UTC 24 Aug 29 03:06:19 AM UTC 24 63483118 ps
T56 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_and_tpm_min_idle.1183246970 Aug 29 03:03:42 AM UTC 24 Aug 29 03:06:20 AM UTC 24 16027258808 ps
T33 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_stress_all.1853510736 Aug 29 03:03:46 AM UTC 24 Aug 29 03:06:20 AM UTC 24 8238255866 ps
T388 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_csb_read.3907122352 Aug 29 03:06:19 AM UTC 24 Aug 29 03:06:22 AM UTC 24 29877964 ps
T194 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_all.2133089482 Aug 29 03:05:24 AM UTC 24 Aug 29 03:06:24 AM UTC 24 12382471972 ps
T277 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_intercept.3960709698 Aug 29 03:05:12 AM UTC 24 Aug 29 03:06:24 AM UTC 24 4477349187 ps
T389 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_sts_read.759636644 Aug 29 03:06:23 AM UTC 24 Aug 29 03:06:25 AM UTC 24 239280148 ps
T390 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_read_buffer_direct.2644101101 Aug 29 03:06:11 AM UTC 24 Aug 29 03:06:26 AM UTC 24 1356684979 ps
T391 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_rw.346075645 Aug 29 03:06:24 AM UTC 24 Aug 29 03:06:26 AM UTC 24 144513720 ps
T392 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_pass_addr_payload_swap.623872022 Aug 29 03:06:25 AM UTC 24 Aug 29 03:06:29 AM UTC 24 32313913 ps
T262 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_intercept.2333331562 Aug 29 03:06:26 AM UTC 24 Aug 29 03:06:34 AM UTC 24 842332666 ps
T280 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_upload.2131636326 Aug 29 03:06:27 AM UTC 24 Aug 29 03:06:35 AM UTC 24 596400767 ps
T259 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_pass_cmd_filtering.1124192566 Aug 29 03:06:25 AM UTC 24 Aug 29 03:06:36 AM UTC 24 253909159 ps
T215 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_and_tpm_min_idle.663021177 Aug 29 03:02:04 AM UTC 24 Aug 29 03:06:36 AM UTC 24 87832905944 ps
T393 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_cfg_cmd.3736363064 Aug 29 03:06:30 AM UTC 24 Aug 29 03:06:37 AM UTC 24 257361595 ps
T282 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_intercept.1385419617 Aug 29 03:05:59 AM UTC 24 Aug 29 03:06:39 AM UTC 24 5910174553 ps
T273 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_mailbox.2387274787 Aug 29 03:06:26 AM UTC 24 Aug 29 03:06:42 AM UTC 24 1704984261 ps
T394 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_read_hw_reg.2403445168 Aug 29 03:06:21 AM UTC 24 Aug 29 03:06:44 AM UTC 24 8351763858 ps
T359 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_all.3182125114 Aug 29 03:06:22 AM UTC 24 Aug 29 03:06:44 AM UTC 24 3032447285 ps
T57 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_and_tpm_min_idle.1893527745 Aug 29 03:05:27 AM UTC 24 Aug 29 03:06:45 AM UTC 24 3026513365 ps
T395 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_alert_test.726234818 Aug 29 03:06:45 AM UTC 24 Aug 29 03:06:47 AM UTC 24 15121456 ps
T396 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_csb_read.3114796082 Aug 29 03:06:45 AM UTC 24 Aug 29 03:06:47 AM UTC 24 20759923 ps
T304 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.613581095 Aug 29 03:05:58 AM UTC 24 Aug 29 03:06:48 AM UTC 24 63468742849 ps
T58 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_all.1347240943 Aug 29 03:07:31 AM UTC 24 Aug 29 03:08:50 AM UTC 24 23216447318 ps
T261 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.2388774379 Aug 29 03:06:36 AM UTC 24 Aug 29 03:06:49 AM UTC 24 6053434972 ps
T397 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.4107021351 Aug 29 03:06:48 AM UTC 24 Aug 29 03:06:51 AM UTC 24 191907032 ps
T398 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_read_buffer_direct.2482704432 Aug 29 03:06:36 AM UTC 24 Aug 29 03:06:51 AM UTC 24 2562493584 ps
T399 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.2735496041 Aug 29 03:06:48 AM UTC 24 Aug 29 03:06:52 AM UTC 24 1329991038 ps
T400 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_rw.3345415740 Aug 29 03:06:49 AM UTC 24 Aug 29 03:06:53 AM UTC 24 75591305 ps
T204 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_and_tpm.938383036 Aug 29 03:05:25 AM UTC 24 Aug 29 03:06:58 AM UTC 24 10158796783 ps
T347 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_all.3577147041 Aug 29 03:06:48 AM UTC 24 Aug 29 03:06:59 AM UTC 24 2947506074 ps
T306 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.3534223541 Aug 29 03:06:50 AM UTC 24 Aug 29 03:07:00 AM UTC 24 2021809424 ps
T401 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_upload.3455373037 Aug 29 03:06:54 AM UTC 24 Aug 29 03:07:03 AM UTC 24 11000541288 ps
T266 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_mode.3353480208 Aug 29 03:06:34 AM UTC 24 Aug 29 03:07:05 AM UTC 24 1283995130 ps
T263 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_mode.3828115998 Aug 29 03:06:59 AM UTC 24 Aug 29 03:07:05 AM UTC 24 71826166 ps
T269 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_cfg_cmd.88846218 Aug 29 03:06:59 AM UTC 24 Aug 29 03:07:06 AM UTC 24 384209179 ps
T402 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.514337421 Aug 29 03:07:01 AM UTC 24 Aug 29 03:07:09 AM UTC 24 241758025 ps
T305 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_mailbox.708717975 Aug 29 03:06:53 AM UTC 24 Aug 29 03:07:09 AM UTC 24 544244410 ps
T295 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_intercept.3772231556 Aug 29 03:06:52 AM UTC 24 Aug 29 03:07:11 AM UTC 24 3159066739 ps
T34 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_stress_all.832906318 Aug 29 03:06:43 AM UTC 24 Aug 29 03:07:13 AM UTC 24 14063683213 ps
T181 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_alert_test.3155618286 Aug 29 03:07:11 AM UTC 24 Aug 29 03:07:13 AM UTC 24 71332238 ps
T182 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_csb_read.73374488 Aug 29 03:07:11 AM UTC 24 Aug 29 03:07:13 AM UTC 24 89563549 ps
T183 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_sts_read.1324011507 Aug 29 03:07:14 AM UTC 24 Aug 29 03:07:16 AM UTC 24 156046474 ps
T184 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_rw.1386031610 Aug 29 03:07:15 AM UTC 24 Aug 29 03:07:18 AM UTC 24 155149560 ps
T185 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_read_hw_reg.2149670411 Aug 29 03:07:14 AM UTC 24 Aug 29 03:07:19 AM UTC 24 358359787 ps
T186 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_pass_addr_payload_swap.1178810184 Aug 29 03:07:17 AM UTC 24 Aug 29 03:07:21 AM UTC 24 52739976 ps
T187 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_pass_cmd_filtering.2295933356 Aug 29 03:07:17 AM UTC 24 Aug 29 03:07:22 AM UTC 24 296760363 ps
T188 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_upload.1457378563 Aug 29 03:07:22 AM UTC 24 Aug 29 03:07:26 AM UTC 24 57527295 ps
T189 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_cfg_cmd.3190001196 Aug 29 03:07:22 AM UTC 24 Aug 29 03:07:27 AM UTC 24 359030901 ps
T355 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_all.2807176344 Aug 29 03:07:14 AM UTC 24 Aug 29 03:07:30 AM UTC 24 755549472 ps
T230 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_and_tpm_min_idle.2987511109 Aug 29 03:07:05 AM UTC 24 Aug 29 03:07:32 AM UTC 24 7624468672 ps
T231 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_mailbox.3475016242 Aug 29 03:06:00 AM UTC 24 Aug 29 03:07:33 AM UTC 24 39987056844 ps
T403 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_and_tpm.3808668680 Aug 29 03:06:38 AM UTC 24 Aug 29 03:07:34 AM UTC 24 20142372278 ps
T265 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_mailbox.1873576842 Aug 29 03:07:20 AM UTC 24 Aug 29 03:07:36 AM UTC 24 586917813 ps
T404 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_read_buffer_direct.2464959479 Aug 29 03:07:27 AM UTC 24 Aug 29 03:07:37 AM UTC 24 186834463 ps
T405 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_alert_test.600218854 Aug 29 03:07:37 AM UTC 24 Aug 29 03:07:39 AM UTC 24 18013102 ps
T406 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_csb_read.1417709451 Aug 29 03:07:38 AM UTC 24 Aug 29 03:07:40 AM UTC 24 16946017 ps
T219 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_intercept.3723397352 Aug 29 03:07:20 AM UTC 24 Aug 29 03:07:42 AM UTC 24 1577757865 ps
T217 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_mode_ignore_cmds.3579285493 Aug 29 03:03:32 AM UTC 24 Aug 29 03:07:45 AM UTC 24 36550910516 ps
T407 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_all.623145654 Aug 29 03:07:43 AM UTC 24 Aug 29 03:07:45 AM UTC 24 31967434 ps
T408 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_sts_read.1918055854 Aug 29 03:07:43 AM UTC 24 Aug 29 03:07:46 AM UTC 24 158501317 ps
T409 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_mode.123513285 Aug 29 03:07:23 AM UTC 24 Aug 29 03:07:46 AM UTC 24 7008201660 ps
T410 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_rw.4192543930 Aug 29 03:07:45 AM UTC 24 Aug 29 03:07:48 AM UTC 24 92048081 ps
T192 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_all.1032877458 Aug 29 03:06:12 AM UTC 24 Aug 29 03:07:49 AM UTC 24 10522930705 ps
T97 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_stress_all.158081869 Aug 29 03:05:30 AM UTC 24 Aug 29 03:07:50 AM UTC 24 8379376629 ps
T241 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.1179300718 Aug 29 03:06:51 AM UTC 24 Aug 29 03:07:51 AM UTC 24 13176155811 ps
T298 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_pass_addr_payload_swap.1964401164 Aug 29 03:07:46 AM UTC 24 Aug 29 03:07:51 AM UTC 24 115464279 ps
T411 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_mailbox.1541946791 Aug 29 03:07:50 AM UTC 24 Aug 29 03:07:54 AM UTC 24 33226317 ps
T283 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_upload.4023227856 Aug 29 03:07:50 AM UTC 24 Aug 29 03:07:55 AM UTC 24 457584429 ps
T107 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_cfg_cmd.1473981460 Aug 29 03:07:51 AM UTC 24 Aug 29 03:07:56 AM UTC 24 119305313 ps
T239 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_intercept.381241283 Aug 29 03:07:46 AM UTC 24 Aug 29 03:07:56 AM UTC 24 553803505 ps
T284 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_pass_cmd_filtering.2058822009 Aug 29 03:07:46 AM UTC 24 Aug 29 03:08:00 AM UTC 24 3408541714 ps
T412 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_read_buffer_direct.1588068757 Aug 29 03:07:55 AM UTC 24 Aug 29 03:08:02 AM UTC 24 1270208570 ps
T413 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_read_hw_reg.715650568 Aug 29 03:07:41 AM UTC 24 Aug 29 03:08:03 AM UTC 24 14209646987 ps
T414 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_alert_test.3927338011 Aug 29 03:08:02 AM UTC 24 Aug 29 03:08:05 AM UTC 24 25331987 ps
T415 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_csb_read.508700425 Aug 29 03:08:04 AM UTC 24 Aug 29 03:08:06 AM UTC 24 44143027 ps
T343 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_mode.354701999 Aug 29 03:07:52 AM UTC 24 Aug 29 03:08:11 AM UTC 24 6002807881 ps
T416 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_sts_read.1010925663 Aug 29 03:08:12 AM UTC 24 Aug 29 03:08:14 AM UTC 24 81508890 ps
T417 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_read_hw_reg.2445288245 Aug 29 03:08:07 AM UTC 24 Aug 29 03:08:16 AM UTC 24 3929039868 ps
T418 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_rw.2883150727 Aug 29 03:08:15 AM UTC 24 Aug 29 03:08:17 AM UTC 24 53160173 ps
T193 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_and_tpm_min_idle.3054276200 Aug 29 03:06:41 AM UTC 24 Aug 29 03:08:30 AM UTC 24 18006058336 ps
T244 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_all.2535861724 Aug 29 03:06:38 AM UTC 24 Aug 29 03:08:30 AM UTC 24 80528510322 ps
T285 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_intercept.568320661 Aug 29 03:08:26 AM UTC 24 Aug 29 03:08:31 AM UTC 24 373977219 ps
T213 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_all.1319897665 Aug 29 03:07:03 AM UTC 24 Aug 29 03:08:31 AM UTC 24 18424075435 ps
T250 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_and_tpm.4169421493 Aug 29 03:07:32 AM UTC 24 Aug 29 03:08:32 AM UTC 24 2501681148 ps
T346 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_all.548225593 Aug 29 03:08:09 AM UTC 24 Aug 29 03:08:33 AM UTC 24 3756739191 ps
T291 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_pass_addr_payload_swap.221265619 Aug 29 03:08:18 AM UTC 24 Aug 29 03:08:34 AM UTC 24 1999146758 ps
T419 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_mode.2296165534 Aug 29 03:08:32 AM UTC 24 Aug 29 03:08:38 AM UTC 24 295457605 ps
T420 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_cfg_cmd.485277420 Aug 29 03:08:31 AM UTC 24 Aug 29 03:08:38 AM UTC 24 196290357 ps
T421 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_read_buffer_direct.2601505712 Aug 29 03:08:33 AM UTC 24 Aug 29 03:08:41 AM UTC 24 630744663 ps
T422 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_alert_test.2389996247 Aug 29 03:08:42 AM UTC 24 Aug 29 03:08:44 AM UTC 24 44116335 ps
T423 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_mode_ignore_cmds.106807961 Aug 29 03:08:32 AM UTC 24 Aug 29 03:08:44 AM UTC 24 2697082503 ps
T220 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_upload.2098623600 Aug 29 03:08:31 AM UTC 24 Aug 29 03:08:46 AM UTC 24 3827234871 ps
T424 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_rw.3186739787 Aug 29 03:08:51 AM UTC 24 Aug 29 03:08:53 AM UTC 24 12612331 ps
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T426 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_sts_read.2084066459 Aug 29 03:08:48 AM UTC 24 Aug 29 03:08:50 AM UTC 24 37656792 ps
T427 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_read_hw_reg.471300303 Aug 29 03:08:47 AM UTC 24 Aug 29 03:08:52 AM UTC 24 1147361335 ps
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T431 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_cfg_cmd.2163749794 Aug 29 03:08:59 AM UTC 24 Aug 29 03:09:11 AM UTC 24 8279550178 ps
T432 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_alert_test.3995570975 Aug 29 03:09:10 AM UTC 24 Aug 29 03:09:13 AM UTC 24 24944107 ps
T433 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_csb_read.4208765800 Aug 29 03:09:12 AM UTC 24 Aug 29 03:09:15 AM UTC 24 47365045 ps
T256 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_intercept.3374488866 Aug 29 03:11:27 AM UTC 24 Aug 29 03:11:33 AM UTC 24 234135044 ps
T434 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_read_buffer_direct.2748449739 Aug 29 03:09:04 AM UTC 24 Aug 29 03:09:16 AM UTC 24 1819465655 ps
T435 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_read_hw_reg.2628249934 Aug 29 03:09:16 AM UTC 24 Aug 29 03:09:18 AM UTC 24 14483204 ps
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