Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	36461	1			T6	16		T8	6		T12	76
auto[SpiFlashAddrCfg]	8186	1			T12	4		T14	4		T16	2
auto[SpiFlashAddr3b]	9940	1			T9	6		T12	2		T18	2
auto[SpiFlashAddr4b]	8337	1			T7	6		T8	2		T12	4

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

36372

1

T6

16

T8

8

T9

6

auto[1]

26552

1

T7

6

T47

20

T38

72

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32685

1

T6

16

T7

4

T8

4

auto[1]

30239

1

T7

2

T8

4

T9

4

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	41429	1			T6	16		T8	6		T12	80
values[1]	1188	1			T9	4		T88	2		T87	2
values[2]	1569	1			T38	5		T39	9		T40	16
values[3]	1583	1			T7	4		T18	2		T47	8
values[4]	1619	1			T7	2		T9	2		T12	4
values[5]	1594	1			T14	3		T18	2		T38	7
values[6]	1579	1			T48	2		T47	2		T38	6
values[7]	1500	1			T14	4		T87	4		T38	15
values[8]	10863	1			T8	2		T12	2		T16	2

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35312

1

T6

16

T7

6

T8

8

auto[1]

27612

1

T14

7

T42

1

T38

160

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

59479

1

T6

16

T7

6

T8

8

write

3445

1

T12

2

T38

13

T39

19

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

20525

1

T6

16

T7

4

T8

2

valids[0x1]

42399

1

T7

2

T8

6

T9

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1666	1			T17	4		T18	2		T38	6
internal_process_ops[0x5a]	1738	1			T48	2		T38	5		T45	1
internal_process_ops[0x05]	21954	1			T8	2		T12	74		T16	2
internal_process_ops[0x35]	1670	1			T47	2		T88	4		T38	10
internal_process_ops[0x15]	1723	1			T8	4		T12	2		T47	2
internal_process_ops[0x03]	1186	1			T9	4		T14	3		T88	2
internal_process_ops[0x0b]	1167	1			T12	4		T87	4		T38	1
internal_process_ops[0x3b]	1174	1			T7	2		T47	8		T38	2
internal_process_ops[0x6b]	1181	1			T7	2		T8	2		T9	2
internal_process_ops[0xbb]	1192	1			T18	2		T38	3		T39	7
internal_process_ops[0xeb]	1209	1			T42	1		T47	2		T38	5

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

61214

1

T6

16

T7

6

T8

8

auto[1]

1710

1

T38

7

T39

10

T40

7

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

60379

1

T6

16

T7

6

T8

8

auto[1]

2545

1

T12

2

T50

2

T38

15

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11458

1

T6

16

T8

6

T12

76

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7240

1

T47

2

T52

4

T39

64

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2418

1

T12

4

T16

2

T88

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

2121

1

T47

2

T52

6

T39

15

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2918

1

T9

6

T12

2

T18

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2592

1

T52

4

T39

22

T49

15

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2440

1

T8

2

T12

2

T18

14

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

2222

1

T7

6

T47

16

T52

8

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

128

1

T39

2

T190

1

T31

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

137

1

T39

1

T44

1

T54

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

99

1

T39

1

T49

2

T43

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

95

1

T49

1

T43

1

T44

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

126

1

T49

2

T191

2

T190

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

104

1

T49

4

T44

1

T54

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

122

1

T39

1

T43

4

T44

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

120

1

T39

1

T43

1

T44

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

125

1

T39

2

T44

1

T190

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

108

1

T43

1

T44

5

T58

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

136

1

T39

3

T43

4

T31

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

117

1

T43

1

T54

1

T56

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

141

1

T12

2

T43

5

T54

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

92

1

T39

3

T49

2

T43

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

116

1

T43

1

T192

1

T193

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

137

1

T39

5

T53

2

T44

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10873

1

T38

48

T45

11

T40

316

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6015

1

T38

25

T45

1

T40

121

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1370

1

T14

4

T38

13

T45

3

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1424

1

T38

15

T45

1

T40

21

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1769

1

T38

10

T46

1

T45

1

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1791

1

T38

14

T45

2

T40

40

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1451

1

T14

3

T42

1

T38

14

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1377

1

T38

8

T45

1

T40

16

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

81

1

T40

1

T85

1

T32

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

104

1

T38

1

T32

1

T194

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

101

1

T38

3

T40

3

T85

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

130

1

T38

2

T40

2

T61

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

95

1

T40

5

T85

7

T31

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

107

1

T40

3

T61

1

T32

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

103

1

T38

1

T61

3

T32

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

76

1

T38

1

T40

1

T85

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

108

1

T38

1

T40

4

T84

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

93

1

T40

1

T85

4

T195

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

88

1

T40

5

T61

3

T31

4

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

95

1

T38

3

T195

2

T194

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

54

1

T38

1

T196

2

T194

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

72

1

T85

2

T195

2

T32

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

112

1

T40

3

T61

1

T84

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

123

1

T85

2

T105

1

T32

2

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	4396	1			T6	16		T18	2		T50	4
auto[0]	values[0]	valids[0x1]	17706	1			T8	6		T12	80		T16	2
auto[0]	values[1]	valids[0x1]	656	1			T9	4		T88	2		T87	2
auto[0]	values[2]	valids[0x0]	636	1			T39	3		T49	6		T43	10
auto[0]	values[2]	valids[0x1]	360	1			T39	6		T49	1		T108	2
auto[0]	values[3]	valids[0x0]	575	1			T7	2		T47	8		T39	2
auto[0]	values[3]	valids[0x1]	375	1			T7	2		T18	2		T88	2
auto[0]	values[4]	valids[0x0]	644	1			T7	2		T9	2		T51	4
auto[0]	values[4]	valids[0x1]	391	1			T12	4		T18	2		T49	2
auto[0]	values[5]	valids[0x0]	613	1			T18	2		T39	6		T49	2
auto[0]	values[5]	valids[0x1]	389	1			T39	2		T49	3		T43	3
auto[0]	values[6]	valids[0x0]	652	1			T47	2		T39	6		T49	7
auto[0]	values[6]	valids[0x1]	323	1			T48	2		T49	2		T43	5
auto[0]	values[7]	valids[0x0]	577	1			T51	2		T39	4		T49	7
auto[0]	values[7]	valids[0x1]	318	1			T87	4		T52	4		T39	1
auto[0]	values[8]	valids[0x0]	4261	1			T8	2		T12	2		T16	2
auto[0]	values[8]	valids[0x1]	2440	1			T18	6		T47	2		T39	14
auto[1]	values[0]	valids[0x0]	3571	1			T38	44		T45	10		T40	60
auto[1]	values[0]	valids[0x1]	15756	1			T38	50		T45	2		T40	428
auto[1]	values[1]	valids[0x1]	532	1			T38	2		T45	3		T40	12
auto[1]	values[2]	valids[0x0]	331	1			T38	2		T40	6		T61	1
auto[1]	values[2]	valids[0x1]	242	1			T38	3		T40	10		T61	1
auto[1]	values[3]	valids[0x0]	377	1			T38	4		T40	10		T61	2
auto[1]	values[3]	valids[0x1]	256	1			T40	5		T85	1		T31	4
auto[1]	values[4]	valids[0x0]	350	1			T38	3		T45	1		T40	13
auto[1]	values[4]	valids[0x1]	234	1			T40	4		T85	3		T31	1
auto[1]	values[5]	valids[0x0]	332	1			T38	2		T40	5		T61	2
auto[1]	values[5]	valids[0x1]	260	1			T14	3		T38	5		T40	1
auto[1]	values[6]	valids[0x0]	393	1			T38	4		T40	3		T84	1
auto[1]	values[6]	valids[0x1]	211	1			T38	2		T40	3		T61	1
auto[1]	values[7]	valids[0x0]	403	1			T14	4		T38	12		T40	5
auto[1]	values[7]	valids[0x1]	202	1			T38	3		T40	1		T61	3
auto[1]	values[8]	valids[0x0]	2414	1			T42	1		T38	15		T46	1
auto[1]	values[8]	valids[0x1]	1748	1			T38	9		T45	2		T40	28