Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3596724

1

T6

297

T7

1

T8

2356

auto[1]

27982

1

T12

72

T50

11

T38

1103

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

917068

1

T6

297

T7

1

T8

464

auto[1]

2707638

1

T8

1892

T12

332

T88

1408

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	708567	1			T6	134		T7	1		T8	1006
auto[524288:1048575]	420642	1			T8	110		T9	89		T14	133
auto[1048576:1572863]	413243	1			T8	54		T9	633		T14	1590
auto[1572864:2097151]	461755	1			T6	5		T8	661		T9	83
auto[2097152:2621439]	430615	1			T8	206		T9	222		T14	485
auto[2621440:3145727]	441231	1			T6	153		T8	29		T9	700
auto[3145728:3670015]	388495	1			T6	3		T8	290		T102	1
auto[3670016:4194303]	360158	1			T6	2		T9	104		T17	186

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2744001

1

T6

66

T7

1

T8

1911

auto[1]

880705

1

T6

231

T8

445

T9

1819

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3081927

1

T6

297

T7

1

T8

2356

auto[1]

542779

1

T38

2009

T39

3023

T40

1171

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	221454	1			T6	134		T7	1		T8	106
auto[0]	auto[0]	auto[0:524287]	auto[1]	438386	1			T8	900		T12	262		T88	1408
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	114098	1			T8	110		T9	89		T14	133
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	259226	1			T38	128		T39	2493		T40	518
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	97321	1			T8	11		T9	633		T14	1590
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	247807	1			T8	43		T38	1		T39	1643
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	106513	1			T6	5		T9	83		T14	101
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	259950	1			T8	661		T38	1793		T40	516
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	87625	1			T8	176		T9	222		T14	485
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	272147	1			T8	30		T39	1281		T40	310
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	99749	1			T6	153		T8	29		T9	700
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	240496	1			T45	128		T39	3		T40	161
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	94641	1			T6	3		T8	32		T102	1
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	234871	1			T8	258		T38	768		T39	256
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	84153	1			T6	2		T9	104		T17	186
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	200120	1			T40	387		T61	257		T49	1824
auto[0]	auto[1]	auto[0:524287]	auto[0]	994	1			T38	23		T39	5		T40	4
auto[0]	auto[1]	auto[0:524287]	auto[1]	43713	1			T38	384		T39	257		T40	1
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	904	1			T38	18		T40	4		T85	10
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	43448	1			T39	2756		T40	512		T44	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	694	1			T38	34		T61	1		T43	3
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	63551	1			T38	128		T61	120		T43	128
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	835	1			T38	4		T195	3		T56	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	90476	1			T44	5130		T195	257		T194	512
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	1143	1			T38	20		T40	3		T61	2
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	66553	1			T38	4		T40	262		T61	2432
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	1335	1			T38	48		T40	4		T85	6
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	95725	1			T38	518		T40	2		T61	4
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	713	1			T40	2		T49	1		T43	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	55824	1			T43	128		T195	1026		T32	2959
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	801	1			T38	12		T40	2		T49	3
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	71458	1			T38	672		T40	256		T49	512
auto[1]	auto[0]	auto[0:524287]	auto[0]	528	1			T12	2		T50	2		T38	13
auto[1]	auto[0]	auto[0:524287]	auto[1]	2780	1			T12	70		T50	9		T38	95
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	400	1			T39	4		T40	1		T43	3
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2135	1			T39	44		T43	9		T84	28
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	469	1			T38	3		T39	1		T40	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	3022	1			T38	334		T40	6		T43	6
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	423	1			T38	10		T40	2		T43	2
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	3057	1			T38	495		T40	84		T43	2
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	380	1			T39	1		T40	1		T61	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2073	1			T39	1		T40	16		T61	8
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	445	1			T38	7		T39	3		T40	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2812	1			T39	86		T40	44		T49	21
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	346	1			T61	2		T49	3		T43	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1665	1			T61	28		T49	74		T43	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	337	1			T38	2		T40	3		T61	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2498	1			T40	28		T61	18		T49	28
auto[1]	auto[1]	auto[0:524287]	auto[0]	78	1			T39	1		T40	1		T43	3
auto[1]	auto[1]	auto[0:524287]	auto[1]	634	1			T39	4		T40	31		T43	88
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	55	1			T44	1		T194	1		T57	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	376	1			T44	21		T194	29		T57	5
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	96	1			T38	14		T54	1		T95	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	283	1			T54	1		T95	22		T33	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	111	1			T38	7		T195	1		T215	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	390	1			T195	1		T97	11		T244	64
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	97	1			T38	9		T40	1		T44	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	597	1			T40	5		T44	6		T31	2
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	132	1			T38	5		T40	2		T32	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	537	1			T40	79		T32	1		T196	6
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	82	1			T195	2		T32	2		T244	4
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	353	1			T195	1		T32	3		T244	111
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	116	1			T38	13		T195	1		T31	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	675	1			T38	96		T195	47		T193	13

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2180805	1			T6	66		T7	1		T8	1911
auto[0]	auto[0]	auto[1]	877752	1			T6	231		T8	445		T9	1819
auto[0]	auto[1]	auto[0]	535925	1			T38	1865		T39	3018		T40	1051
auto[0]	auto[1]	auto[1]	2242	1			T40	1		T43	2		T195	2
auto[1]	auto[0]	auto[0]	22794	1			T12	72		T50	9		T38	956
auto[1]	auto[0]	auto[1]	576	1			T50	2		T38	3		T40	2
auto[1]	auto[1]	auto[0]	4477	1			T38	141		T39	5		T40	118
auto[1]	auto[1]	auto[1]	135	1			T38	3		T40	1		T43	1