Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2952856	1			T2	1		T3	1		T4	1
all_pins[1]	2952856	1			T2	1		T3	1		T4	1
all_pins[2]	2952856	1			T2	1		T3	1		T4	1
all_pins[3]	2952856	1			T2	1		T3	1		T4	1
all_pins[4]	2952856	1			T2	1		T3	1		T4	1
all_pins[5]	2952856	1			T2	1		T3	1		T4	1
all_pins[6]	2952856	1			T2	1		T3	1		T4	1
all_pins[7]	2952856	1			T2	1		T3	1		T4	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	23612150	1			T2	8		T3	8		T4	8
values[0x1]	10698	1			T21	32		T32	194		T33	17
transitions[0x0=>0x1]	9791	1			T21	20		T32	187		T33	12
transitions[0x1=>0x0]	9804	1			T21	20		T32	187		T33	12

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2952372	1			T2	1		T3	1		T4	1
all_pins[0]	values[0x1]	484	1			T21	3		T32	23		T34	3
all_pins[0]	transitions[0x0=>0x1]	247	1			T21	1		T32	23		T34	3
all_pins[0]	transitions[0x1=>0x0]	177	1			T21	2		T32	3		T33	2
all_pins[1]	values[0x0]	2952442	1			T2	1		T3	1		T4	1
all_pins[1]	values[0x1]	414	1			T21	4		T32	3		T33	2
all_pins[1]	transitions[0x0=>0x1]	293	1			T21	3		T32	3		T33	2
all_pins[1]	transitions[0x1=>0x0]	281	1			T21	2		T32	3		T33	1
all_pins[2]	values[0x0]	2952454	1			T2	1		T3	1		T4	1
all_pins[2]	values[0x1]	402	1			T21	3		T32	3		T33	1
all_pins[2]	transitions[0x0=>0x1]	369	1			T32	1		T34	1		T173	28
all_pins[2]	transitions[0x1=>0x0]	145	1			T21	3		T32	2		T33	3
all_pins[3]	values[0x0]	2952678	1			T2	1		T3	1		T4	1
all_pins[3]	values[0x1]	178	1			T21	6		T32	4		T33	4
all_pins[3]	transitions[0x0=>0x1]	124	1			T21	4		T32	2		T33	2
all_pins[3]	transitions[0x1=>0x0]	158	1			T21	3		T32	2		T34	3
all_pins[4]	values[0x0]	2952644	1			T2	1		T3	1		T4	1
all_pins[4]	values[0x1]	212	1			T21	5		T32	4		T33	2
all_pins[4]	transitions[0x0=>0x1]	165	1			T21	3		T32	3		T33	1
all_pins[4]	transitions[0x1=>0x0]	2078	1			T21	2		T32	146		T33	2
all_pins[5]	values[0x0]	2950731	1			T2	1		T3	1		T4	1
all_pins[5]	values[0x1]	2125	1			T21	4		T32	147		T33	3
all_pins[5]	transitions[0x0=>0x1]	1795	1			T21	3		T32	146		T33	2
all_pins[5]	transitions[0x1=>0x0]	6386	1			T21	3		T32	4		T33	3
all_pins[6]	values[0x0]	2946140	1			T2	1		T3	1		T4	1
all_pins[6]	values[0x1]	6716	1			T21	4		T32	5		T33	4
all_pins[6]	transitions[0x0=>0x1]	6673	1			T21	3		T32	4		T33	4
all_pins[6]	transitions[0x1=>0x0]	124	1			T21	2		T32	4		T33	1
all_pins[7]	values[0x0]	2952689	1			T2	1		T3	1		T4	1
all_pins[7]	values[0x1]	167	1			T21	3		T32	5		T33	1
all_pins[7]	transitions[0x0=>0x1]	125	1			T21	3		T32	5		T33	1
all_pins[7]	transitions[0x1=>0x0]	455	1			T21	3		T32	23		T34	3