Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20195

1

T6

16

T8

8

T9

6

auto[1]

15117

1

T7

6

T47

20

T52

22

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4172	1			T65	8		T108	22		T43	20
values[1]	3778	1			T6	16		T47	20		T51	10
values[2]	4323	1			T18	20		T88	10		T50	15
values[3]	4109	1			T39	110		T63	2		T49	36
values[4]	4878	1			T7	6		T9	6		T87	8
values[5]	4523	1			T16	4		T17	4		T49	96
values[6]	5151	1			T52	22		T39	37		T49	63
values[7]	4378	1			T8	8		T12	86		T48	2

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4594	1			T7	6		T9	6		T16	4
values[1]	4116	1			T50	15		T53	6		T43	100
values[2]	4606	1			T6	16		T12	86		T39	22
values[3]	4816	1			T18	20		T87	8		T49	117
values[4]	4168	1			T17	4		T51	10		T65	8
values[5]	4177	1			T39	62		T49	40		T191	14
values[6]	4082	1			T39	141		T49	20		T43	140
values[7]	4753	1			T8	8		T48	2		T88	10

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	399	1			T44	14		T54	12		T267	20
auto[0]	values[0]	values[1]	235	1			T43	8		T192	15		T193	11
auto[0]	values[0]	values[2]	235	1			T108	22		T54	9		T268	12
auto[0]	values[0]	values[3]	130	1			T242	15		T236	8		T251	13
auto[0]	values[0]	values[4]	312	1			T65	8		T44	12		T173	9
auto[0]	values[0]	values[5]	300	1			T56	6		T173	26		T175	16
auto[0]	values[0]	values[6]	356	1			T54	19		T269	4		T240	22
auto[0]	values[0]	values[7]	473	1			T193	8		T175	25		T268	247
auto[0]	values[1]	values[0]	273	1			T39	9		T49	13		T43	12
auto[0]	values[1]	values[1]	204	1			T43	19		T33	13		T262	12
auto[0]	values[1]	values[2]	242	1			T6	16		T31	11		T56	11
auto[0]	values[1]	values[3]	269	1			T215	16		T192	9		T175	7
auto[0]	values[1]	values[4]	265	1			T51	10		T174	13		T242	10
auto[0]	values[1]	values[5]	284	1			T39	11		T226	14		T176	14
auto[0]	values[1]	values[6]	231	1			T31	31		T192	10		T249	47
auto[0]	values[1]	values[7]	240	1			T54	14		T31	9		T192	9
auto[0]	values[2]	values[0]	144	1			T39	11		T221	11		T270	11
auto[0]	values[2]	values[1]	500	1			T50	15		T43	22		T44	30
auto[0]	values[2]	values[2]	341	1			T190	13		T58	13		T227	7
auto[0]	values[2]	values[3]	433	1			T18	20		T49	11		T192	24
auto[0]	values[2]	values[4]	191	1			T31	23		T271	10		T35	17
auto[0]	values[2]	values[5]	282	1			T226	7		T247	10		T233	12
auto[0]	values[2]	values[6]	316	1			T220	10		T173	9		T240	4
auto[0]	values[2]	values[7]	348	1			T88	10		T272	10		T273	6
auto[0]	values[3]	values[0]	314	1			T43	13		T57	21		T212	17
auto[0]	values[3]	values[1]	153	1			T54	12		T210	12		T208	13
auto[0]	values[3]	values[2]	212	1			T63	2		T33	23		T57	9
auto[0]	values[3]	values[3]	347	1			T56	10		T242	12		T236	8
auto[0]	values[3]	values[4]	216	1			T44	14		T274	18		T252	69
auto[0]	values[3]	values[5]	299	1			T275	10		T58	11		T210	23
auto[0]	values[3]	values[6]	426	1			T39	99		T175	13		T144	11
auto[0]	values[3]	values[7]	239	1			T49	30		T58	11		T174	14
auto[0]	values[4]	values[0]	239	1			T9	6		T43	18		T219	12
auto[0]	values[4]	values[1]	448	1			T212	10		T236	16		T258	12
auto[0]	values[4]	values[2]	325	1			T43	11		T44	14		T31	9
auto[0]	values[4]	values[3]	435	1			T87	8		T253	14		T261	11
auto[0]	values[4]	values[4]	211	1			T43	13		T57	8		T107	14
auto[0]	values[4]	values[5]	467	1			T191	14		T43	23		T44	32
auto[0]	values[4]	values[6]	356	1			T39	28		T49	11		T276	4
auto[0]	values[4]	values[7]	394	1			T277	12		T268	11		T236	10
auto[0]	values[5]	values[0]	400	1			T16	4		T49	16		T58	8
auto[0]	values[5]	values[1]	289	1			T193	15		T173	13		T278	14
auto[0]	values[5]	values[2]	288	1			T279	4		T215	12		T250	14
auto[0]	values[5]	values[3]	429	1			T49	13		T229	20		T280	2
auto[0]	values[5]	values[4]	644	1			T17	4		T44	96		T54	7
auto[0]	values[5]	values[5]	252	1			T56	12		T58	12		T274	7
auto[0]	values[5]	values[6]	173	1			T43	7		T174	10		T210	14
auto[0]	values[5]	values[7]	249	1			T49	10		T54	19		T226	8
auto[0]	values[6]	values[0]	399	1			T43	10		T281	8		T250	7
auto[0]	values[6]	values[1]	343	1			T193	9		T258	72		T144	27
auto[0]	values[6]	values[2]	308	1			T234	24		T54	10		T31	61
auto[0]	values[6]	values[3]	299	1			T190	6		T215	12		T282	8
auto[0]	values[6]	values[4]	371	1			T33	10		T57	32		T175	10
auto[0]	values[6]	values[5]	380	1			T39	4		T49	15		T44	13
auto[0]	values[6]	values[6]	278	1			T43	16		T283	2		T240	12
auto[0]	values[6]	values[7]	404	1			T49	31		T56	15		T193	10
auto[0]	values[7]	values[0]	224	1			T44	40		T242	8		T233	20
auto[0]	values[7]	values[1]	312	1			T43	9		T175	14		T242	11
auto[0]	values[7]	values[2]	497	1			T12	86		T39	15		T260	12
auto[0]	values[7]	values[3]	381	1			T55	9		T56	17		T284	12
auto[0]	values[7]	values[4]	355	1			T190	8		T175	14		T236	11
auto[0]	values[7]	values[5]	182	1			T49	11		T31	12		T55	12
auto[0]	values[7]	values[6]	270	1			T215	16		T285	8		T286	10
auto[0]	values[7]	values[7]	384	1			T8	8		T48	2		T44	116
auto[1]	values[0]	values[0]	296	1			T44	33		T54	14		T192	6
auto[1]	values[0]	values[1]	247	1			T43	12		T192	5		T193	9
auto[1]	values[0]	values[2]	245	1			T54	11		T268	8		T236	4
auto[1]	values[0]	values[3]	172	1			T242	8		T236	42		T251	40
auto[1]	values[0]	values[4]	234	1			T44	8		T173	32		T287	10
auto[1]	values[0]	values[5]	154	1			T56	14		T173	8		T175	4
auto[1]	values[0]	values[6]	165	1			T54	5		T240	7		T175	9
auto[1]	values[0]	values[7]	219	1			T193	12		T175	15		T268	19
auto[1]	values[1]	values[0]	431	1			T47	20		T39	41		T49	7
auto[1]	values[1]	values[1]	161	1			T43	10		T33	13		T212	6
auto[1]	values[1]	values[2]	239	1			T31	32		T56	20		T174	11
auto[1]	values[1]	values[3]	201	1			T215	6		T192	28		T175	17
auto[1]	values[1]	values[4]	227	1			T174	7		T242	35		T221	10
auto[1]	values[1]	values[5]	121	1			T39	14		T226	6		T176	9
auto[1]	values[1]	values[6]	182	1			T31	12		T192	10		T249	13
auto[1]	values[1]	values[7]	208	1			T54	8		T31	11		T192	66
auto[1]	values[2]	values[0]	134	1			T39	10		T221	9		T270	17
auto[1]	values[2]	values[1]	148	1			T43	8		T44	6		T193	18
auto[1]	values[2]	values[2]	436	1			T190	7		T58	7		T227	13
auto[1]	values[2]	values[3]	321	1			T49	86		T288	10		T192	16
auto[1]	values[2]	values[4]	130	1			T31	5		T271	10		T35	11
auto[1]	values[2]	values[5]	214	1			T226	13		T247	10		T233	8
auto[1]	values[2]	values[6]	172	1			T173	11		T240	25		T221	11
auto[1]	values[2]	values[7]	213	1			T249	8		T178	3		T274	24
auto[1]	values[3]	values[0]	152	1			T43	10		T57	6		T212	12
auto[1]	values[3]	values[1]	219	1			T54	8		T210	8		T208	46
auto[1]	values[3]	values[2]	146	1			T33	4		T57	11		T226	7
auto[1]	values[3]	values[3]	321	1			T56	17		T242	33		T236	27
auto[1]	values[3]	values[4]	113	1			T44	6		T289	18		T274	9
auto[1]	values[3]	values[5]	205	1			T58	9		T210	10		T258	12
auto[1]	values[3]	values[6]	422	1			T39	11		T175	7		T144	114
auto[1]	values[3]	values[7]	325	1			T49	6		T58	61		T174	6
auto[1]	values[4]	values[0]	249	1			T7	6		T43	4		T212	92
auto[1]	values[4]	values[1]	218	1			T212	10		T236	4		T258	10
auto[1]	values[4]	values[2]	396	1			T43	30		T44	20		T31	22
auto[1]	values[4]	values[3]	284	1			T261	9		T193	1		T227	4
auto[1]	values[4]	values[4]	199	1			T43	7		T57	12		T175	18
auto[1]	values[4]	values[5]	224	1			T43	10		T44	5		T190	7
auto[1]	values[4]	values[6]	227	1			T39	3		T49	9		T193	11
auto[1]	values[4]	values[7]	206	1			T268	9		T236	45		T176	4
auto[1]	values[5]	values[0]	257	1			T49	33		T58	12		T192	9
auto[1]	values[5]	values[1]	120	1			T193	5		T173	7		T242	12
auto[1]	values[5]	values[2]	266	1			T215	13		T250	7		T212	13
auto[1]	values[5]	values[3]	318	1			T49	7		T241	16		T193	8
auto[1]	values[5]	values[4]	222	1			T44	8		T54	13		T31	12
auto[1]	values[5]	values[5]	212	1			T56	8		T58	8		T274	87
auto[1]	values[5]	values[6]	222	1			T43	104		T174	10		T210	10
auto[1]	values[5]	values[7]	182	1			T49	17		T54	6		T226	12
auto[1]	values[6]	values[0]	489	1			T52	22		T43	10		T250	13
auto[1]	values[6]	values[1]	296	1			T53	6		T193	65		T258	15
auto[1]	values[6]	values[2]	208	1			T54	10		T31	5		T33	11
auto[1]	values[6]	values[3]	286	1			T190	14		T215	8		T192	8
auto[1]	values[6]	values[4]	171	1			T238	8		T33	15		T57	5
auto[1]	values[6]	values[5]	372	1			T39	33		T49	5		T44	14
auto[1]	values[6]	values[6]	185	1			T43	13		T290	2		T240	8
auto[1]	values[6]	values[7]	362	1			T49	12		T56	5		T193	28
auto[1]	values[7]	values[0]	194	1			T44	9		T242	12		T233	8
auto[1]	values[7]	values[1]	223	1			T43	12		T175	29		T242	9
auto[1]	values[7]	values[2]	222	1			T39	7		T62	4		T260	8
auto[1]	values[7]	values[3]	190	1			T55	11		T56	3		T193	4
auto[1]	values[7]	values[4]	307	1			T190	12		T291	8		T175	17
auto[1]	values[7]	values[5]	229	1			T49	9		T31	80		T55	8
auto[1]	values[7]	values[6]	101	1			T215	9		T236	7		T292	6
auto[1]	values[7]	values[7]	307	1			T44	13		T31	27		T57	7