Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

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Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	396	1			T8	2		T39	1		T49	3
auto[ReadAddrCrossIntoMailbox]	344	1			T39	2		T49	1		T43	3
auto[ReadAddrCrossOutOfMailbox]	326	1			T39	2		T49	3		T43	3
auto[ReadAddrCrossAllMailbox]	262	1			T39	1		T49	5		T43	2
auto[ReadAddrOutsideMailbox]	4273	1			T7	4		T9	6		T12	6

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2699

1

T7

2

T8

1

T9

3

auto[1]

2902

1

T7

2

T8

1

T9

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	932	1			T9	4		T88	2		T52	4
read_ops[0x0b]	948	1			T12	4		T87	4		T39	4
read_ops[0x3b]	906	1			T7	2		T47	8		T51	4
read_ops[0x6b]	914	1			T7	2		T8	2		T9	2
read_ops[0xbb]	924	1			T18	2		T39	7		T49	11
read_ops[0xeb]	977	1			T47	2		T51	2		T39	4

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T39	1		T43	1		T54	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	38	1			T49	2		T215	1		T193	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T39	1		T192	1		T293	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	31	1			T33	1		T192	1		T174	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	18	1			T58	1		T192	1		T293	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	31	1			T43	1		T56	1		T215	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	31	1			T39	1		T193	2		T174	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	22	1			T227	1		T144	1		T294	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	321	1			T9	2		T88	1		T52	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	381	1			T9	2		T88	1		T52	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	26	1			T31	1		T33	1		T193	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T43	1		T190	1		T174	3
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	29	1			T193	1		T212	3		T226	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T227	2		T242	1		T249	2
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T193	1		T208	1		T268	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T57	2		T173	1		T249	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	23	1			T56	1		T33	1		T175	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	31	1			T49	1		T43	1		T190	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	366	1			T12	2		T87	2		T39	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	363	1			T12	2		T87	2		T39	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	36	1			T49	1		T33	1		T58	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	25	1			T295	1		T173	1		T296	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T43	1		T54	2		T193	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	37	1			T39	1		T43	2		T192	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	26	1			T43	1		T174	1		T144	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T57	1		T249	1		T210	2
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T49	2		T56	1		T226	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	25	1			T43	1		T190	1		T193	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	318	1			T7	1		T47	4		T51	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	369	1			T7	1		T47	4		T51	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	38	1			T8	1		T56	1		T33	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	34	1			T8	1		T190	1		T265	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	14	1			T54	1		T57	1		T236	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	35	1			T192	2		T249	1		T226	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	26	1			T56	2		T175	1		T268	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T39	1		T192	1		T173	2
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T174	1		T242	1		T249	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T44	1		T226	1		T297	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	337	1			T7	1		T9	1		T12	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	370	1			T7	1		T9	1		T12	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	28	1			T56	1		T262	3		T295	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	37	1			T43	1		T56	1		T262	3
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T49	1		T193	1		T175	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T56	1		T144	1		T297	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T39	1		T49	2		T43	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	32	1			T215	2		T255	1		T175	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T49	1		T57	1		T192	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	22	1			T249	1		T226	2		T144	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	361	1			T18	1		T39	1		T49	4
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	351	1			T18	1		T39	5		T49	3
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	34	1			T44	1		T215	1		T265	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	36	1			T57	1		T265	2		T247	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	38	1			T56	1		T192	1		T227	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	34	1			T54	1		T250	1		T255	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	29	1			T54	1		T265	1		T192	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	30	1			T49	1		T265	1		T192	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T54	1		T265	1		T210	2
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T49	1		T54	1		T265	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	367	1			T47	1		T51	1		T39	3
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	369	1			T47	1		T51	1		T39	1