Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3981	1			T39	50		T62	4		T44	36
values[1]	4130	1			T9	6		T43	20		T44	101
values[2]	5204	1			T16	4		T48	2		T47	20
values[3]	4018	1			T7	6		T49	40		T43	62
values[4]	4743	1			T18	20		T87	8		T50	15
values[5]	4651	1			T12	86		T51	10		T52	22
values[6]	4100	1			T6	16		T17	4		T39	25
values[7]	4485	1			T8	8		T39	31		T65	8

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4735	1			T47	20		T88	10		T39	110
values[1]	4106	1			T49	43		T43	30		T44	193
values[2]	4083	1			T51	10		T52	22		T49	97
values[3]	4421	1			T18	20		T39	87		T49	20
values[4]	4230	1			T7	6		T39	52		T49	49
values[5]	4570	1			T6	16		T87	8		T50	15
values[6]	4652	1			T12	86		T16	4		T17	4
values[7]	4515	1			T8	8		T9	6		T48	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34402

1

T6

16

T7

6

T8

8

auto[1]

910

1

T39

10

T49

7

T53

2

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	450	1			T62	4		T298	2		T193	20
auto[0]	values[0]	values[1]	579	1			T31	43		T55	20		T299	6
auto[0]	values[0]	values[2]	248	1			T250	20		T240	29		T175	20
auto[0]	values[0]	values[3]	424	1			T39	45		T215	25		T193	20
auto[0]	values[0]	values[4]	609	1			T33	26		T236	25		T258	95
auto[0]	values[0]	values[5]	665	1			T44	35		T31	90		T239	10
auto[0]	values[0]	values[6]	437	1			T31	19		T215	22		T210	24
auto[0]	values[0]	values[7]	467	1			T215	22		T236	48		T203	19
auto[0]	values[1]	values[0]	651	1			T54	26		T192	20		T220	10
auto[0]	values[1]	values[1]	565	1			T54	43		T31	30		T249	60
auto[0]	values[1]	values[2]	420	1			T44	33		T249	29		T210	23
auto[0]	values[1]	values[3]	584	1			T44	45		T54	19		T256	16
auto[0]	values[1]	values[4]	431	1			T174	21		T242	22		T300	6
auto[0]	values[1]	values[5]	557	1			T190	20		T58	20		T207	20
auto[0]	values[1]	values[6]	427	1			T44	20		T57	20		T58	20
auto[0]	values[1]	values[7]	387	1			T9	6		T43	20		T238	8
auto[0]	values[2]	values[0]	630	1			T47	20		T88	10		T44	20
auto[0]	values[2]	values[1]	705	1			T33	25		T58	71		T174	26
auto[0]	values[2]	values[2]	515	1			T193	124		T301	20		T251	61
auto[0]	values[2]	values[3]	481	1			T39	35		T31	23		T58	20
auto[0]	values[2]	values[4]	664	1			T43	21		T229	20		T295	4
auto[0]	values[2]	values[5]	527	1			T39	22		T44	19		T231	6
auto[0]	values[2]	values[6]	865	1			T16	4		T108	22		T56	20
auto[0]	values[2]	values[7]	653	1			T48	2		T54	22		T31	37
auto[0]	values[3]	values[0]	370	1			T43	20		T192	20		T193	20
auto[0]	values[3]	values[1]	404	1			T44	109		T175	53		T226	18
auto[0]	values[3]	values[2]	474	1			T43	39		T56	20		T192	35
auto[0]	values[3]	values[3]	663	1			T49	20		T54	19		T58	68
auto[0]	values[3]	values[4]	496	1			T7	6		T54	18		T31	42
auto[0]	values[3]	values[5]	539	1			T49	19		T190	20		T54	22
auto[0]	values[3]	values[6]	487	1			T208	63		T144	20		T177	27
auto[0]	values[3]	values[7]	483	1			T56	24		T262	12		T302	12
auto[0]	values[4]	values[0]	589	1			T49	23		T191	14		T43	20
auto[0]	values[4]	values[1]	628	1			T55	20		T58	19		T192	40
auto[0]	values[4]	values[2]	653	1			T192	17		T193	79		T212	97
auto[0]	values[4]	values[3]	545	1			T18	20		T57	19		T193	20
auto[0]	values[4]	values[4]	397	1			T39	20		T230	20		T192	20
auto[0]	values[4]	values[5]	458	1			T87	8		T50	15		T49	19
auto[0]	values[4]	values[6]	702	1			T253	14		T227	20		T175	72
auto[0]	values[4]	values[7]	660	1			T43	110		T44	20		T241	14
auto[0]	values[5]	values[0]	641	1			T39	108		T49	20		T31	28
auto[0]	values[5]	values[1]	316	1			T49	43		T57	20		T303	2
auto[0]	values[5]	values[2]	428	1			T51	10		T52	22		T267	20
auto[0]	values[5]	values[3]	653	1			T43	23		T280	2		T173	34
auto[0]	values[5]	values[4]	520	1			T49	48		T43	20		T55	19
auto[0]	values[5]	values[5]	792	1			T175	18		T208	51		T212	47
auto[0]	values[5]	values[6]	610	1			T12	86		T304	12		T175	47
auto[0]	values[5]	values[7]	568	1			T288	10		T258	86		T144	20
auto[0]	values[6]	values[0]	711	1			T190	20		T215	20		T305	4
auto[0]	values[6]	values[1]	440	1			T43	29		T44	82		T33	20
auto[0]	values[6]	values[2]	645	1			T234	24		T56	31		T208	20
auto[0]	values[6]	values[3]	455	1			T272	10		T193	37		T208	20
auto[0]	values[6]	values[4]	319	1			T276	4		T306	12		T212	49
auto[0]	values[6]	values[5]	452	1			T6	16		T31	65		T255	10
auto[0]	values[6]	values[6]	409	1			T17	4		T39	25		T190	20
auto[0]	values[6]	values[7]	565	1			T63	2		T43	91		T44	26
auto[0]	values[7]	values[0]	573	1			T65	8		T49	36		T44	35
auto[0]	values[7]	values[1]	385	1			T282	8		T230	20		T278	14
auto[0]	values[7]	values[2]	593	1			T49	97		T275	10		T277	12
auto[0]	values[7]	values[3]	502	1			T218	16		T273	6		T175	40
auto[0]	values[7]	values[4]	682	1			T39	31		T43	20		T260	20
auto[0]	values[7]	values[5]	442	1			T57	20		T269	4		T227	20
auto[0]	values[7]	values[6]	591	1			T53	4		T44	47		T56	19
auto[0]	values[7]	values[7]	621	1			T8	8		T49	20		T54	19
auto[1]	values[0]	values[0]	10	1			T307	3		T308	1		T309	4
auto[1]	values[0]	values[1]	12	1			T144	1		T310	2		T311	3
auto[1]	values[0]	values[2]	5	1			T69	1		T312	1		T313	2
auto[1]	values[0]	values[3]	10	1			T39	5		T236	3		T247	1
auto[1]	values[0]	values[4]	11	1			T236	1		T310	3		T314	2
auto[1]	values[0]	values[5]	19	1			T44	1		T31	2		T291	2
auto[1]	values[0]	values[6]	20	1			T31	1		T215	3		T76	1
auto[1]	values[0]	values[7]	15	1			T236	2		T203	1		T315	1
auto[1]	values[1]	values[0]	13	1			T174	2		T271	1		T268	2
auto[1]	values[1]	values[1]	11	1			T54	2		T31	1		T69	1
auto[1]	values[1]	values[2]	20	1			T44	1		T249	2		T251	1
auto[1]	values[1]	values[3]	11	1			T44	2		T54	1		T297	1
auto[1]	values[1]	values[4]	13	1			T242	1		T316	2		T317	1
auto[1]	values[1]	values[5]	22	1			T242	3		T144	1		T178	5
auto[1]	values[1]	values[6]	9	1			T193	3		T210	1		T318	5
auto[1]	values[1]	values[7]	9	1			T192	1		T252	1		T80	1
auto[1]	values[2]	values[0]	21	1			T144	3		T224	1		T319	3
auto[1]	values[2]	values[1]	14	1			T58	1		T174	1		T221	1
auto[1]	values[2]	values[2]	19	1			T251	3		T297	4		T320	2
auto[1]	values[2]	values[3]	30	1			T39	2		T192	2		T210	1
auto[1]	values[2]	values[4]	15	1			T43	1		T193	1		T245	4
auto[1]	values[2]	values[5]	24	1			T44	1		T250	2		T321	4
auto[1]	values[2]	values[6]	23	1			T178	2		T322	2		T323	2
auto[1]	values[2]	values[7]	18	1			T54	2		T31	1		T57	1
auto[1]	values[3]	values[0]	8	1			T43	1		T212	2		T324	1
auto[1]	values[3]	values[1]	7	1			T226	2		T247	2		T297	1
auto[1]	values[3]	values[2]	11	1			T43	2		T192	2		T208	2
auto[1]	values[3]	values[3]	17	1			T54	1		T58	5		T210	2
auto[1]	values[3]	values[4]	19	1			T54	2		T31	1		T56	1
auto[1]	values[3]	values[5]	19	1			T49	1		T249	3		T210	2
auto[1]	values[3]	values[6]	9	1			T208	2		T311	1		T325	1
auto[1]	values[3]	values[7]	12	1			T56	3		T233	1		T76	1
auto[1]	values[4]	values[0]	14	1			T49	4		T326	2		T327	2
auto[1]	values[4]	values[1]	13	1			T58	1		T193	1		T328	2
auto[1]	values[4]	values[2]	15	1			T192	3		T212	2		T319	2
auto[1]	values[4]	values[3]	10	1			T57	1		T144	2		T228	1
auto[1]	values[4]	values[4]	13	1			T39	1		T174	3		T289	4
auto[1]	values[4]	values[5]	16	1			T49	1		T156	2		T80	2
auto[1]	values[4]	values[6]	13	1			T175	3		T144	1		T270	1
auto[1]	values[4]	values[7]	17	1			T43	1		T241	2		T175	3
auto[1]	values[5]	values[0]	27	1			T39	2		T193	2		T212	1
auto[1]	values[5]	values[1]	7	1			T144	3		T329	4		-	-
auto[1]	values[5]	values[2]	10	1			T330	2		T331	1		T332	1
auto[1]	values[5]	values[3]	15	1			T242	2		T226	1		T333	1
auto[1]	values[5]	values[4]	14	1			T49	1		T55	1		T271	4
auto[1]	values[5]	values[5]	20	1			T175	2		T208	1		T212	2
auto[1]	values[5]	values[6]	21	1			T175	6		T274	3		T251	3
auto[1]	values[5]	values[7]	9	1			T258	1		T334	4		T335	2
auto[1]	values[6]	values[0]	17	1			T192	2		T175	2		T212	1
auto[1]	values[6]	values[1]	13	1			T43	1		T44	2		T69	2
auto[1]	values[6]	values[2]	19	1			T212	6		T236	2		T178	1
auto[1]	values[6]	values[3]	14	1			T193	1		T258	3		T144	1
auto[1]	values[6]	values[4]	11	1			T212	1		T69	1		T310	2
auto[1]	values[6]	values[5]	13	1			T31	1		T35	2		T292	2
auto[1]	values[6]	values[6]	5	1			T308	1		T336	1		T332	3
auto[1]	values[6]	values[7]	12	1			T44	1		T261	1		T208	2
auto[1]	values[7]	values[0]	10	1			T44	2		T250	1		T337	1
auto[1]	values[7]	values[1]	7	1			T174	1		T226	1		T221	1
auto[1]	values[7]	values[2]	8	1			T252	3		T338	1		T339	1
auto[1]	values[7]	values[3]	7	1			T228	2		T69	1		T311	2
auto[1]	values[7]	values[4]	16	1			T55	2		T228	2		T320	2
auto[1]	values[7]	values[5]	5	1			T212	1		T178	1		T317	1
auto[1]	values[7]	values[6]	24	1			T53	2		T44	2		T56	1
auto[1]	values[7]	values[7]	19	1			T54	1		T193	1		T268	3