Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	745	1			T21	14		T32	14		T33	10
all_values[1]	745	1			T21	14		T32	14		T33	10
all_values[2]	745	1			T21	14		T32	14		T33	10
all_values[3]	745	1			T21	14		T32	14		T33	10
all_values[4]	745	1			T21	14		T32	14		T33	10
all_values[5]	745	1			T21	14		T32	14		T33	10
all_values[6]	745	1			T21	14		T32	14		T33	10
all_values[7]	745	1			T21	14		T32	14		T33	10

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3165

1

T21

59

T32

55

T33

45

auto[1]

2795

1

T21

53

T32

57

T33

35

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2371

1

T21

44

T32

42

T33

38

auto[1]

3589

1

T21

68

T32

70

T33

42

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3410

1

T21

62

T32

66

T33

47

auto[1]

2550

1

T21

50

T32

46

T33

33

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	168	1			T21	6		T33	7		T34	2
all_values[0]	auto[0]	auto[0]	auto[1]	74	1			T21	2		T32	2		T173	2
all_values[0]	auto[0]	auto[1]	auto[0]	143	1			T21	3		T32	2		T33	1
all_values[0]	auto[0]	auto[1]	auto[1]	67	1			T21	1		T32	1		T34	3
all_values[0]	auto[1]	auto[0]	auto[1]	168	1			T21	1		T32	4		T33	2
all_values[0]	auto[1]	auto[1]	auto[1]	125	1			T21	1		T32	5		T34	5
all_values[1]	auto[0]	auto[0]	auto[0]	130	1			T21	2		T32	5		T33	1
all_values[1]	auto[0]	auto[0]	auto[1]	71	1			T21	2		T32	1		T33	1
all_values[1]	auto[0]	auto[1]	auto[0]	126	1			T21	2		T32	3		T34	1
all_values[1]	auto[0]	auto[1]	auto[1]	90	1			T21	1		T33	3		T173	2
all_values[1]	auto[1]	auto[0]	auto[1]	169	1			T21	4		T32	3		T33	5
all_values[1]	auto[1]	auto[1]	auto[1]	159	1			T21	3		T32	2		T34	5
all_values[2]	auto[0]	auto[0]	auto[0]	145	1			T21	2		T32	4		T33	3
all_values[2]	auto[0]	auto[0]	auto[1]	79	1			T21	4		T32	1		T33	1
all_values[2]	auto[0]	auto[1]	auto[0]	132	1			T21	3		T32	4		T33	2
all_values[2]	auto[0]	auto[1]	auto[1]	68	1			T32	2		T34	1		T96	2
all_values[2]	auto[1]	auto[0]	auto[1]	190	1			T21	2		T32	2		T33	3
all_values[2]	auto[1]	auto[1]	auto[1]	131	1			T21	3		T32	1		T33	1
all_values[3]	auto[0]	auto[0]	auto[0]	155	1			T21	2		T32	6		T33	3
all_values[3]	auto[0]	auto[0]	auto[1]	74	1			T32	1		T34	2		T173	5
all_values[3]	auto[0]	auto[1]	auto[0]	135	1			T21	4		T32	2		T33	2
all_values[3]	auto[0]	auto[1]	auto[1]	71	1			T21	1		T32	2		T33	1
all_values[3]	auto[1]	auto[0]	auto[1]	163	1			T21	2		T32	1		T34	2
all_values[3]	auto[1]	auto[1]	auto[1]	147	1			T21	5		T32	2		T33	4
all_values[4]	auto[0]	auto[0]	auto[0]	154	1			T21	2		T32	2		T33	2
all_values[4]	auto[0]	auto[0]	auto[1]	62	1			T32	1		T34	1		T174	3
all_values[4]	auto[0]	auto[1]	auto[0]	128	1			T21	3		T32	3		T33	3
all_values[4]	auto[0]	auto[1]	auto[1]	98	1			T21	1		T32	2		T33	1
all_values[4]	auto[1]	auto[0]	auto[1]	155	1			T21	4		T32	2		T33	3
all_values[4]	auto[1]	auto[1]	auto[1]	148	1			T21	4		T32	4		T33	1
all_values[5]	auto[0]	auto[0]	auto[0]	200	1			T21	4		T32	2		T33	3
all_values[5]	auto[0]	auto[1]	auto[0]	192	1			T21	1		T32	7		T33	3
all_values[5]	auto[1]	auto[0]	auto[1]	189	1			T21	4		T32	2		T33	2
all_values[5]	auto[1]	auto[1]	auto[1]	164	1			T21	5		T32	3		T33	2
all_values[6]	auto[0]	auto[0]	auto[0]	147	1			T21	1		T32	1		T33	1
all_values[6]	auto[0]	auto[0]	auto[1]	77	1			T21	2		T32	3		T34	2
all_values[6]	auto[0]	auto[1]	auto[0]	127	1			T21	3		T33	1		T34	4
all_values[6]	auto[0]	auto[1]	auto[1]	65	1			T21	2		T32	2		T33	2
all_values[6]	auto[1]	auto[0]	auto[1]	186	1			T21	4		T32	5		T33	3
all_values[6]	auto[1]	auto[1]	auto[1]	143	1			T21	2		T32	3		T33	3
all_values[7]	auto[0]	auto[0]	auto[0]	160	1			T21	4		T33	4		T34	3
all_values[7]	auto[0]	auto[0]	auto[1]	79	1			T21	1		T32	4		T34	1
all_values[7]	auto[0]	auto[1]	auto[0]	129	1			T21	2		T32	1		T33	2
all_values[7]	auto[0]	auto[1]	auto[1]	64	1			T21	1		T32	2		T34	1
all_values[7]	auto[1]	auto[0]	auto[1]	170	1			T21	4		T32	3		T33	1
all_values[7]	auto[1]	auto[1]	auto[1]	143	1			T21	2		T32	4		T33	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal