Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1845

1

T4

4

T5

2

T15

7

auto[1]

1770

1

T4

4

T15

7

T24

5

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2054

1

T5

2

T15

14

T27

8

auto[1]

1561

1

T4

8

T24

13

T26

17

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2844

1

T4

8

T5

1

T15

10

auto[1]

771

1

T5

1

T15

4

T27

2

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	719	1			T4	2		T15	1		T24	1
valid[1]	728	1			T5	1		T15	4		T24	1
valid[2]	763	1			T4	2		T15	2		T24	3
valid[3]	711	1			T4	1		T5	1		T15	3
valid[4]	694	1			T4	3		T15	4		T24	2

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	133	1			T15	1		T43	1		T105	3
auto[0]	auto[0]	valid[0]	auto[1]	150	1			T4	1		T24	1		T26	3
auto[0]	auto[0]	valid[1]	auto[0]	141	1			T15	2		T27	1		T39	1
auto[0]	auto[0]	valid[1]	auto[1]	163	1			T26	1		T28	4		T29	3
auto[0]	auto[0]	valid[2]	auto[0]	137	1			T15	1		T60	2		T43	2
auto[0]	auto[0]	valid[2]	auto[1]	159	1			T4	1		T24	2		T26	4
auto[0]	auto[0]	valid[3]	auto[0]	125	1			T5	1		T15	1		T64	1
auto[0]	auto[0]	valid[3]	auto[1]	148	1			T24	5		T26	1		T28	1
auto[0]	auto[0]	valid[4]	auto[0]	122	1			T39	1		T43	1		T105	1
auto[0]	auto[0]	valid[4]	auto[1]	155	1			T4	2		T26	1		T28	4
auto[0]	auto[1]	valid[0]	auto[0]	121	1			T27	1		T43	3		T105	2
auto[0]	auto[1]	valid[0]	auto[1]	161	1			T4	1		T26	3		T28	1
auto[0]	auto[1]	valid[1]	auto[0]	116	1			T15	1		T27	2		T37	1
auto[0]	auto[1]	valid[1]	auto[1]	151	1			T24	1		T26	1		T28	3
auto[0]	auto[1]	valid[2]	auto[0]	134	1			T15	1		T64	1		T104	1
auto[0]	auto[1]	valid[2]	auto[1]	164	1			T4	1		T24	1		T28	1
auto[0]	auto[1]	valid[3]	auto[0]	120	1			T27	1		T64	1		T43	1
auto[0]	auto[1]	valid[3]	auto[1]	161	1			T4	1		T24	1		T26	2
auto[0]	auto[1]	valid[4]	auto[0]	134	1			T15	3		T27	1		T39	1
auto[0]	auto[1]	valid[4]	auto[1]	149	1			T4	1		T24	2		T26	1
auto[1]	auto[0]	valid[0]	auto[0]	77	1			T27	1		T30	1		T39	1
auto[1]	auto[0]	valid[1]	auto[0]	87	1			T5	1		T37	1		T39	2
auto[1]	auto[0]	valid[2]	auto[0]	86	1			T39	1		T104	1		T43	1
auto[1]	auto[0]	valid[3]	auto[0]	92	1			T15	2		T44	1		T356	2
auto[1]	auto[0]	valid[4]	auto[0]	70	1			T27	1		T39	1		T44	1
auto[1]	auto[1]	valid[0]	auto[0]	77	1			T32	1		T196	1		T56	1
auto[1]	auto[1]	valid[1]	auto[0]	70	1			T15	1		T64	1		T43	2
auto[1]	auto[1]	valid[2]	auto[0]	83	1			T39	1		T64	1		T354	2
auto[1]	auto[1]	valid[3]	auto[0]	65	1			T104	1		T43	1		T356	1
auto[1]	auto[1]	valid[4]	auto[0]	64	1			T15	1		T37	1		T44	2

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal