Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

51609

1

T5

10

T15

242

T25

8

auto[1]

16771

1

T4

8

T24

13

T26

189

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49571

1

T4

8

T5

5

T15

157

auto[1]

18809

1

T5

5

T15

85

T25

5

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	35226	1			T4	8		T5	9		T15	116
others[1]	5736	1			T15	16		T25	1		T26	10
others[2]	5748	1			T5	1		T15	22		T25	1
others[3]	6513	1			T15	19		T25	2		T26	19
interest[1]	3737	1			T15	22		T25	2		T26	7
interest[4]	23035	1			T4	8		T5	4		T15	81
interest[64]	11420	1			T15	47		T26	27		T27	32

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	16774	1			T5	4		T15	73		T27	76
auto[0]	auto[0]	others[1]	2765	1			T15	11		T25	1		T27	17
auto[0]	auto[0]	others[2]	2731	1			T5	1		T15	10		T25	1
auto[0]	auto[0]	others[3]	3147	1			T15	13		T27	11		T37	10
auto[0]	auto[0]	interest[1]	1797	1			T15	14		T25	1		T27	7
auto[0]	auto[0]	interest[4]	10945	1			T5	2		T15	50		T27	56
auto[0]	auto[0]	interest[64]	5586	1			T15	36		T27	20		T30	1
auto[0]	auto[1]	others[0]	8793	1			T4	8		T24	13		T26	104
auto[0]	auto[1]	others[1]	1375	1			T26	10		T28	33		T103	15
auto[0]	auto[1]	others[2]	1366	1			T26	22		T28	45		T103	15
auto[0]	auto[1]	others[3]	1585	1			T26	19		T28	43		T103	13
auto[0]	auto[1]	interest[1]	902	1			T26	7		T28	33		T103	6
auto[0]	auto[1]	interest[4]	5761	1			T4	8		T24	13		T26	71
auto[0]	auto[1]	interest[64]	2750	1			T26	27		T28	76		T103	25
auto[1]	auto[0]	others[0]	9659	1			T5	5		T15	43		T25	2
auto[1]	auto[0]	others[1]	1596	1			T15	5		T27	5		T37	5
auto[1]	auto[0]	others[2]	1651	1			T15	12		T27	4		T37	2
auto[1]	auto[0]	others[3]	1781	1			T15	6		T25	2		T27	3
auto[1]	auto[0]	interest[1]	1038	1			T15	8		T25	1		T27	4
auto[1]	auto[0]	interest[4]	6329	1			T5	2		T15	31		T25	1
auto[1]	auto[0]	interest[64]	3084	1			T15	11		T27	12		T30	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal