Unified Coverage Report :: Cond split page

Go back

 LINE       19544
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T6,T7,T8
1	1	Covered	T9,T16,T102

 LINE       19544
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T6,T7,T8
1	1	Covered	T9,T16,T39

 LINE       19544
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T9,T12,T50
1	1	Covered	T18,T38,T86

 LINE       19544
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T9,T12,T50
1	1	Covered	T9,T12,T16

 LINE       19544
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T50,T38,T86
1	1	Covered	T9,T12,T18

 LINE       19544
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T50,T38,T39
1	1	Covered	T12,T16,T18

 LINE       19544
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T6,T7,T8
1	1	Covered	T102,T86,T39

 LINE       19544
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T6,T7,T8
1	1	Covered	T9,T16,T102

 LINE       19544
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T6,T7,T8
1	1	Covered	T9,T86,T39

 LINE       19544
 SUB-EXPRESSION (addr_hit[22] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T6,T7,T8
1	1	Covered	T9,T102,T86

 LINE       19544
 SUB-EXPRESSION (addr_hit[23] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T6,T7,T8
1	1	Covered	T9,T16,T102

 LINE       19544
 SUB-EXPRESSION (addr_hit[24] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T6,T7,T8
1	1	Covered	T9,T18,T86

 LINE       19544
 SUB-EXPRESSION (addr_hit[25] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T6,T7,T8
1	1	Covered	T9,T18,T102

 LINE       19544
 SUB-EXPRESSION (addr_hit[26] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T6,T7,T8
1	1	Covered	T9,T18,T102

 LINE       19544
 SUB-EXPRESSION (addr_hit[27] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T6,T7,T8
1	1	Covered	T39,T114,T117

 LINE       19544
 SUB-EXPRESSION (addr_hit[28] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T6,T7,T8
1	1	Covered	T16,T18,T86

 LINE       19544
 SUB-EXPRESSION (addr_hit[29] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T6,T7,T8
1	1	Covered	T102,T39,T114

 LINE       19544
 SUB-EXPRESSION (addr_hit[30] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T6,T7,T8
1	1	Covered	T9,T16,T39

 LINE       19544
 SUB-EXPRESSION (addr_hit[31] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T6,T7,T8
1	1	Covered	T9,T16,T18

 LINE       19544
 SUB-EXPRESSION (addr_hit[32] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T6,T7,T8
1	1	Covered	T9,T102,T39

 LINE       19544
 SUB-EXPRESSION (addr_hit[33] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T6,T7,T8
1	1	Covered	T9,T16,T102

 LINE       19544
 SUB-EXPRESSION (addr_hit[34] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T6,T7,T8
1	1	Covered	T18,T86,T39

 LINE       19544
 SUB-EXPRESSION (addr_hit[35] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T6,T7,T8
1	1	Covered	T9,T102,T86

 LINE       19544
 SUB-EXPRESSION (addr_hit[36] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T6,T7,T8
1	1	Covered	T18,T106,T39

 LINE       19544
 SUB-EXPRESSION (addr_hit[37] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T6,T7,T8
1	1	Covered	T86,T39,T114

 LINE       19544
 SUB-EXPRESSION (addr_hit[38] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T6,T7,T8
1	1	Covered	T9,T86,T39

 LINE       19544
 SUB-EXPRESSION (addr_hit[39] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T6,T7,T8
1	1	Covered	T9,T18,T19

 LINE       19544
 SUB-EXPRESSION (addr_hit[40] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T6,T7,T8
1	1	Covered	T16,T18,T102

 LINE       19544
 SUB-EXPRESSION (addr_hit[41] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T6,T7,T8
1	1	Covered	T9,T18,T86

 LINE       19544
 SUB-EXPRESSION (addr_hit[42] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T6,T7,T8
1	1	Covered	T9,T86,T39

 LINE       19544
 SUB-EXPRESSION (addr_hit[43] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T6,T7,T8
1	1	Covered	T9,T102,T86

 LINE       19544
 SUB-EXPRESSION (addr_hit[44] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T6,T7,T8
1	1	Covered	T9,T18,T102

 LINE       19544
 SUB-EXPRESSION (addr_hit[45] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T6,T7,T8
1	1	Covered	T9,T18,T102

 LINE       19544
 SUB-EXPRESSION (addr_hit[46] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T6,T7,T8
1	1	Covered	T9,T102,T29

 LINE       19544
 SUB-EXPRESSION (addr_hit[47] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T6,T7,T8
1	1	Covered	T9,T18,T102

 LINE       19544
 SUB-EXPRESSION (addr_hit[48] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T6,T7,T8
1	1	Covered	T9,T18,T102

 LINE       19544
 SUB-EXPRESSION (addr_hit[49] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T6,T7,T8
1	1	Covered	T86,T116,T39

 LINE       19544
 SUB-EXPRESSION (addr_hit[50] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T6,T7,T8
1	1	Covered	T102,T86,T39

 LINE       19544
 SUB-EXPRESSION (addr_hit[51] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T6,T7,T8
1	1	Covered	T9,T18,T102

 LINE       19544
 SUB-EXPRESSION (addr_hit[52] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T6,T7,T8
1	1	Covered	T9,T102,T106

 LINE       19544
 SUB-EXPRESSION (addr_hit[53] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T6,T7,T8
1	1	Covered	T9,T16,T102

 LINE       19544
 SUB-EXPRESSION (addr_hit[54] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T6,T7,T8
1	1	Covered	T9,T16,T39

 LINE       19544
 SUB-EXPRESSION (addr_hit[55] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T6,T12,T102
1	1	Covered	T86,T39,T115

 LINE       19544
 SUB-EXPRESSION (addr_hit[56] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T6,T12,T16
1	1	Covered	T9,T39,T114

 LINE       19544
 SUB-EXPRESSION (addr_hit[57] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T6,T102,T38
1	1	Covered	T9,T86,T106

 LINE       19544
 SUB-EXPRESSION (addr_hit[58] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T6,T102,T38
1	1	Covered	T9,T86,T39

 LINE       19544
 SUB-EXPRESSION (addr_hit[59] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T39,T118,T43
1	1	Covered	T9,T18,T86

 LINE       19544
 SUB-EXPRESSION (addr_hit[60] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T4,T5,T9
1	1	Covered	T2,T16,T18

 LINE       19544
 SUB-EXPRESSION (addr_hit[61] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T5,T15,T25
1	1	Covered	T16,T18,T106

 LINE       19544
 SUB-EXPRESSION (addr_hit[62] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T4,T15,T24
1	1	Covered	T9,T102,T39

 LINE       19544
 SUB-EXPRESSION (addr_hit[63] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T4,T9,T15
1	1	Covered	T10,T16,T39

 LINE       19544
 SUB-EXPRESSION (addr_hit[64] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T4,T15,T24
1	1	Covered	T9,T86,T39

 LINE       19544
 SUB-EXPRESSION (addr_hit[65] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T15,T26,T27
1	1	Covered	T9,T18,T102

 LINE       19544
 SUB-EXPRESSION (addr_hit[66] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T15,T26,T27
1	1	Covered	T16,T102,T39

 LINE       19544
 SUB-EXPRESSION (addr_hit[67] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T9,T15,T18
1	1	Covered	T9,T86,T39

 LINE       19544
 SUB-EXPRESSION (addr_hit[68] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T15,T26,T27
1	1	Covered	T9,T18,T102

 LINE       19544
 SUB-EXPRESSION (addr_hit[69] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T15,T26,T27
1	1	Covered	T102,T89,T39

 LINE       19544
 SUB-EXPRESSION (addr_hit[70] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T9,T15,T18
1	1	Covered	T9,T16,T86

 LINE       19544
 SUB-EXPRESSION (addr_hit[71] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T5,T15,T25
1	1	Covered	T5,T9,T15

 LINE       19544
 SUB-EXPRESSION (addr_hit[72] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T5,T15,T25
1	1	Covered	T9,T106,T39

 LINE       19621
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T110,T111,T119
1	1	1	Covered	T5,T11,T12

 LINE       19636
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T9,T16,T39
1	1	0	Covered	T92,T110,T119
1	1	1	Covered	T21,T32,T33

 LINE       19653
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T9,T16,T18
1	1	0	Covered	T120,T119,T121
1	1	1	Covered	T21,T32,T33

 LINE       19670
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T23,T16,T102
1	1	0	Covered	T92,T120,T119
1	1	1	Covered	T23,T90,T91

 LINE       19673
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T6,T7,T8
1	1	0	Covered	T92,T120,T121
1	1	1	Covered	T6,T7,T8

 LINE       19680
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T6,T8,T9
1	1	0	Covered	T110,T111,T120
1	1	1	Covered	T6,T8,T9

 LINE       19687
 EXPRESSION (addr_hit[6] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T13,T89
1	1	0	Covered	T122
1	1	1	Covered	T2,T13,T89

 LINE       19688
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T6,T8,T9
1	1	0	Covered	T110,T111,T119
1	1	1	Covered	T6,T8,T9

 LINE       19697
 EXPRESSION (addr_hit[8] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T6,T7,T8
1	1	0	Not Covered
1	1	1	Covered	T6,T102,T38

 LINE       19698
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T6,T7,T8
1	1	0	Covered	T111,T119,T123
1	1	1	Covered	T6,T7,T8

 LINE       19701
 EXPRESSION (addr_hit[9] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T6,T7,T8
1	1	0	Not Covered
1	1	1	Covered	T6,T7,T8

 LINE       19702
 EXPRESSION (addr_hit[10] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T6,T7,T8
1	1	0	Not Covered
1	1	1	Covered	T6,T7,T8

 LINE       19703
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T6,T7,T8
1	1	0	Covered	T92,T110,T119
1	1	1	Covered	T6,T8,T9

 LINE       19710
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T6,T7,T8
1	1	0	Covered	T92,T110,T124
1	1	1	Covered	T6,T7,T8

 LINE       19715
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T6,T7,T8
1	1	0	Covered	T120,T119,T125
1	1	1	Covered	T6,T7,T8

 LINE       19720
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T6,T7,T8
1	1	0	Covered	T92,T111,T119
1	1	1	Covered	T6,T7,T8

 LINE       19723
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T6,T7,T8
1	1	0	Covered	T92,T120,T119
1	1	1	Covered	T6,T7,T8

 LINE       19726
 EXPRESSION (addr_hit[17] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T9,T12,T18
1	1	0	Not Covered
1	1	1	Covered	T12,T50,T38

 LINE       19727
 EXPRESSION (addr_hit[18] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T12,T16,T18
1	1	0	Not Covered
1	1	1	Covered	T12,T50,T38

 LINE       19728
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T6,T7,T8
1	1	0	Covered	T110,T111,T120
1	1	1	Covered	T6,T7,T8

 LINE       19793
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T6,T7,T8
1	1	0	Covered	T111,T125,T121
1	1	1	Covered	T6,T7,T8

 LINE       19858
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T6,T7,T8
1	1	0	Covered	T120,T119,T121
1	1	1	Covered	T6,T7,T8

 LINE       19923
 EXPRESSION (addr_hit[22] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T6,T7,T8
1	1	0	Covered	T110,T111,T119
1	1	1	Covered	T6,T7,T8

 LINE       19988
 EXPRESSION (addr_hit[23] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T6,T7,T8
1	1	0	Covered	T110,T119,T121
1	1	1	Covered	T6,T7,T8

 LINE       20053
 EXPRESSION (addr_hit[24] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T6,T7,T8
1	1	0	Covered	T92,T110,T119
1	1	1	Covered	T6,T7,T8

 LINE       20118
 EXPRESSION (addr_hit[25] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T6,T7,T8
1	1	0	Covered	T111,T119,T121
1	1	1	Covered	T6,T7,T8

 LINE       20183
 EXPRESSION (addr_hit[26] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T6,T7,T8
1	1	0	Covered	T92,T110,T120
1	1	1	Covered	T6,T7,T8

 LINE       20248
 EXPRESSION (addr_hit[27] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T6,T7,T8
1	1	0	Covered	T110,T111,T119
1	1	1	Covered	T6,T7,T8

 LINE       20251
 EXPRESSION (addr_hit[28] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T6,T7,T8
1	1	0	Covered	T92,T111,T119
1	1	1	Covered	T6,T7,T8

 LINE       20254
 EXPRESSION (addr_hit[29] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T6,T7,T8
1	1	0	Covered	T111,T119,T125
1	1	1	Covered	T6,T7,T8

 LINE       20257
 EXPRESSION (addr_hit[30] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T6,T7,T8
1	1	0	Covered	T110,T119,T126
1	1	1	Covered	T6,T7,T8

 LINE       20260
 EXPRESSION (addr_hit[31] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T6,T7,T8
1	1	0	Covered	T119,T125,T123
1	1	1	Covered	T6,T7,T8