Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3195844	1			T1	1		T2	1		T3	52
all_values[1]	3195844	1			T1	1		T2	1		T3	52
all_values[2]	3195844	1			T1	1		T2	1		T3	52
all_values[3]	3195844	1			T1	1		T2	1		T3	52
all_values[4]	3195844	1			T1	1		T2	1		T3	52
all_values[5]	3195844	1			T1	1		T2	1		T3	52
all_values[6]	3195844	1			T1	1		T2	1		T3	52
all_values[7]	3195844	1			T1	1		T2	1		T3	52

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24549484

1

T1

8

T2

8

T3

416

auto[1]

1017268

1

T34

37

T35

35

T37

36431

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25539251

1

T1

8

T2

8

T3

416

auto[1]

27501

1

T49

144

T34

134

T72

208

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	3021418	1			T1	1		T2	1		T3	52
all_values[0]	auto[0]	auto[1]	13196	1			T49	85		T34	53		T72	95
all_values[0]	auto[1]	auto[0]	160680	1			T34	1		T35	3		T37	5199
all_values[0]	auto[1]	auto[1]	550	1			T34	1		T35	1		T37	5
all_values[1]	auto[0]	auto[0]	3166493	1			T1	1		T2	1		T3	52
all_values[1]	auto[0]	auto[1]	8596	1			T49	59		T34	32		T72	76
all_values[1]	auto[1]	auto[0]	20408	1			T34	4		T35	3		T37	5200
all_values[1]	auto[1]	auto[1]	347	1			T34	1		T35	3		T37	3
all_values[2]	auto[0]	auto[0]	3157213	1			T1	1		T2	1		T3	52
all_values[2]	auto[0]	auto[1]	2878	1			T34	26		T72	37		T35	3
all_values[2]	auto[1]	auto[0]	35444	1			T34	3		T35	3		T37	5202
all_values[2]	auto[1]	auto[1]	309	1			T35	1		T37	1		T38	54
all_values[3]	auto[0]	auto[0]	3137111	1			T1	1		T2	1		T3	52
all_values[3]	auto[0]	auto[1]	160	1			T34	1		T35	3		T38	4
all_values[3]	auto[1]	auto[0]	58410	1			T34	2		T35	3		T37	5204
all_values[3]	auto[1]	auto[1]	163	1			T34	3		T35	2		T37	4
all_values[4]	auto[0]	auto[0]	3022549	1			T1	1		T2	1		T3	52
all_values[4]	auto[0]	auto[1]	172	1			T34	2		T35	2		T37	5
all_values[4]	auto[1]	auto[0]	172957	1			T34	3		T35	2		T37	5199
all_values[4]	auto[1]	auto[1]	166	1			T34	1		T35	3		T37	5
all_values[5]	auto[0]	auto[0]	3015168	1			T1	1		T2	1		T3	52
all_values[5]	auto[0]	auto[1]	138	1			T34	2		T35	3		T37	4
all_values[5]	auto[1]	auto[0]	180381	1			T34	3		T35	4		T37	5195
all_values[5]	auto[1]	auto[1]	157	1			T34	1		T35	1		T37	2
all_values[6]	auto[0]	auto[0]	3007691	1			T1	1		T2	1		T3	52
all_values[6]	auto[0]	auto[1]	177	1			T34	4		T35	4		T37	4
all_values[6]	auto[1]	auto[0]	187815	1			T34	3		T35	1		T37	5201
all_values[6]	auto[1]	auto[1]	161	1			T34	2		T35	2		T37	5
all_values[7]	auto[0]	auto[0]	2996374	1			T1	1		T2	1		T3	52
all_values[7]	auto[0]	auto[1]	150	1			T35	1		T37	5		T38	3
all_values[7]	auto[1]	auto[0]	199139	1			T34	4		T35	2		T37	3
all_values[7]	auto[1]	auto[1]	181	1			T34	5		T35	1		T37	3