Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.04 98.38 93.99 98.62 89.36 97.19 95.45 99.26


Total tests in report: 1131
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
64.98 64.98 92.15 92.15 80.08 80.08 84.06 84.06 26.67 26.67 89.08 89.08 71.83 71.83 10.99 10.99 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_upload.296832309
78.53 13.55 95.28 3.13 86.49 6.42 84.06 0.00 75.56 48.89 93.17 4.09 81.22 9.39 33.91 22.92 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_and_tpm_min_idle.1450363895
82.09 3.56 97.07 1.79 88.73 2.24 88.19 4.13 82.22 6.67 95.47 2.30 84.35 3.13 38.56 4.65 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_all.3535898173
85.18 3.10 97.14 0.07 88.91 0.17 88.58 0.39 82.22 0.00 95.59 0.12 84.64 0.28 59.21 20.64 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_stress_all.2188472031
87.41 2.23 97.36 0.22 89.16 0.25 88.58 0.00 91.11 8.89 95.84 0.25 84.64 0.00 65.20 5.99 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_mode_ignore_cmds.662863083
89.28 1.87 97.81 0.45 90.23 1.07 90.16 1.57 91.11 0.00 96.40 0.56 84.78 0.14 74.50 9.31 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_stress_all.2714002774
90.66 1.37 97.83 0.02 90.30 0.07 90.75 0.59 91.11 0.00 96.43 0.03 92.75 7.97 75.45 0.94 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_intg_err.2922239148
91.34 0.68 97.84 0.02 90.30 0.00 95.47 4.72 91.11 0.00 96.43 0.00 92.75 0.00 75.45 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_ram_cfg.1245827071
91.98 0.64 97.93 0.08 90.40 0.10 95.67 0.20 93.33 2.22 96.50 0.07 92.75 0.00 77.28 1.83 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_and_tpm_min_idle.2090953992
92.58 0.60 97.93 0.00 91.22 0.82 96.46 0.79 93.33 0.00 96.53 0.03 93.46 0.71 79.16 1.88 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.1422750187
93.16 0.58 97.93 0.00 91.22 0.00 96.85 0.39 93.33 0.00 96.53 0.00 93.46 0.00 82.82 3.66 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_stress_all.2494182469
93.73 0.56 98.23 0.30 92.82 1.60 97.05 0.20 93.33 0.00 96.97 0.44 94.17 0.71 83.51 0.69 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_mode.2120769103
94.12 0.39 98.23 0.00 92.84 0.01 97.05 0.00 93.33 0.00 96.97 0.00 94.17 0.00 86.24 2.72 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_and_tpm_min_idle.1201641319
94.44 0.33 98.23 0.00 92.84 0.00 97.05 0.00 93.33 0.00 96.97 0.00 94.17 0.00 88.51 2.28 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_stress_all.1055994020
94.70 0.26 98.23 0.00 92.86 0.02 98.43 1.38 93.33 0.00 96.97 0.00 94.31 0.14 88.76 0.25 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_sec_cm.2456451374
94.92 0.22 98.23 0.00 92.86 0.00 98.43 0.00 93.33 0.00 96.97 0.00 94.31 0.00 90.30 1.53 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_and_tpm.4217204166
95.12 0.20 98.23 0.00 92.86 0.00 98.43 0.00 93.33 0.00 96.97 0.00 94.31 0.00 91.68 1.39 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_stress_all.3999568209
95.29 0.17 98.23 0.00 92.86 0.00 98.43 0.00 93.33 0.00 96.97 0.00 94.31 0.00 92.87 1.19 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_stress_all.971232676
95.44 0.15 98.23 0.00 93.46 0.60 98.43 0.00 93.33 0.00 97.01 0.03 94.31 0.00 93.32 0.45 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_mode_ignore_cmds.4168563257
95.56 0.13 98.23 0.00 93.48 0.02 98.43 0.00 93.33 0.00 97.01 0.00 95.16 0.85 93.32 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.4261873489
95.68 0.11 98.23 0.00 93.48 0.00 98.43 0.00 93.33 0.00 97.01 0.00 95.16 0.00 94.11 0.79 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_all.3030024743
95.78 0.11 98.23 0.00 93.48 0.00 98.43 0.00 93.33 0.00 97.01 0.00 95.31 0.14 94.70 0.59 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_stress_all.2537783353
95.87 0.09 98.31 0.08 93.62 0.14 98.43 0.00 93.33 0.00 97.16 0.15 95.31 0.00 94.95 0.25 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_pass_cmd_filtering.1314876878
95.96 0.08 98.31 0.00 93.62 0.00 98.43 0.00 93.33 0.00 97.16 0.00 95.31 0.00 95.54 0.59 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_mode_ignore_cmds.2385789804
96.02 0.06 98.31 0.00 93.63 0.01 98.43 0.00 93.33 0.00 97.16 0.00 95.31 0.00 95.94 0.40 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_read_hw_reg.3353224194
96.07 0.06 98.31 0.00 93.63 0.00 98.43 0.00 93.33 0.00 97.16 0.00 95.31 0.00 96.34 0.40 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_and_tpm_min_idle.2797925940
96.12 0.05 98.31 0.00 93.65 0.01 98.43 0.00 93.33 0.00 97.16 0.00 95.45 0.14 96.53 0.20 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_stress_all.3400909077
96.16 0.04 98.31 0.00 93.65 0.00 98.43 0.00 93.33 0.00 97.16 0.00 95.45 0.00 96.83 0.30 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_and_tpm.354710542
96.21 0.04 98.31 0.00 93.65 0.00 98.43 0.00 93.33 0.00 97.16 0.00 95.45 0.00 97.13 0.30 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_all.570980436
96.25 0.04 98.33 0.02 93.67 0.02 98.43 0.00 93.33 0.00 97.16 0.00 95.45 0.00 97.38 0.25 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_stress_all.1876364407
96.29 0.04 98.36 0.03 93.71 0.04 98.62 0.20 93.33 0.00 97.16 0.00 95.45 0.00 97.38 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_alert_test.2951614903
96.32 0.04 98.36 0.00 93.71 0.00 98.62 0.00 93.33 0.00 97.16 0.00 95.45 0.00 97.62 0.25 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_all.2007583938
96.34 0.02 98.36 0.00 93.87 0.16 98.62 0.00 93.33 0.00 97.16 0.00 95.45 0.00 97.62 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_errors.1916768083
96.37 0.02 98.36 0.00 93.92 0.05 98.62 0.00 93.33 0.00 97.16 0.00 95.45 0.00 97.72 0.10 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_mode.306394332
96.39 0.02 98.36 0.00 93.92 0.00 98.62 0.00 93.33 0.00 97.16 0.00 95.45 0.00 97.87 0.15 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.437053927
96.41 0.02 98.36 0.00 93.92 0.00 98.62 0.00 93.33 0.00 97.16 0.00 95.45 0.00 98.02 0.15 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_mode_ignore_cmds.3363670062
96.43 0.02 98.36 0.00 93.92 0.00 98.62 0.00 93.33 0.00 97.16 0.00 95.45 0.00 98.17 0.15 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_and_tpm_min_idle.454765527
96.45 0.02 98.37 0.02 93.96 0.04 98.62 0.00 93.33 0.00 97.18 0.02 95.45 0.00 98.22 0.05 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_intercept.583680337
96.46 0.01 98.37 0.00 93.96 0.00 98.62 0.00 93.33 0.00 97.18 0.00 95.45 0.00 98.32 0.10 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_mode.763701984
96.48 0.01 98.37 0.00 93.96 0.00 98.62 0.00 93.33 0.00 97.18 0.00 95.45 0.00 98.42 0.10 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_mode_ignore_cmds.2836088430
96.49 0.01 98.37 0.00 93.96 0.00 98.62 0.00 93.33 0.00 97.18 0.00 95.45 0.00 98.51 0.10 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_mode_ignore_cmds.2152470944
96.50 0.01 98.37 0.00 93.96 0.00 98.62 0.00 93.33 0.00 97.18 0.00 95.45 0.00 98.61 0.10 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_stress_all.1613413405
96.52 0.01 98.37 0.00 93.96 0.00 98.62 0.00 93.33 0.00 97.18 0.00 95.45 0.00 98.71 0.10 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_and_tpm.2639667440
96.53 0.01 98.37 0.00 93.98 0.02 98.62 0.00 93.33 0.00 97.18 0.00 95.45 0.00 98.76 0.05 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_errors.2137533516
96.54 0.01 98.37 0.00 93.98 0.00 98.62 0.00 93.33 0.00 97.18 0.00 95.45 0.00 98.81 0.05 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_intg_err.1408206312
96.54 0.01 98.37 0.00 93.98 0.00 98.62 0.00 93.33 0.00 97.18 0.00 95.45 0.00 98.86 0.05 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_intg_err.4083208709
96.55 0.01 98.37 0.00 93.98 0.00 98.62 0.00 93.33 0.00 97.18 0.00 95.45 0.00 98.91 0.05 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_and_tpm.3927801901
96.56 0.01 98.37 0.00 93.98 0.00 98.62 0.00 93.33 0.00 97.18 0.00 95.45 0.00 98.96 0.05 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_mode.1848624409
96.56 0.01 98.37 0.00 93.98 0.00 98.62 0.00 93.33 0.00 97.18 0.00 95.45 0.00 99.01 0.05 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_all.943399112
96.57 0.01 98.37 0.00 93.98 0.00 98.62 0.00 93.33 0.00 97.18 0.00 95.45 0.00 99.06 0.05 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_and_tpm_min_idle.2800060828
96.58 0.01 98.37 0.00 93.98 0.00 98.62 0.00 93.33 0.00 97.18 0.00 95.45 0.00 99.11 0.05 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_and_tpm.121937171
96.58 0.01 98.37 0.00 93.98 0.00 98.62 0.00 93.33 0.00 97.18 0.00 95.45 0.00 99.16 0.05 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_and_tpm.1216603501
96.59 0.01 98.37 0.00 93.98 0.00 98.62 0.00 93.33 0.00 97.18 0.00 95.45 0.00 99.21 0.05 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_mode.1887116534
96.60 0.01 98.37 0.00 93.98 0.00 98.62 0.00 93.33 0.00 97.18 0.00 95.45 0.00 99.26 0.05 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_upload.2907528168
96.60 0.01 98.38 0.01 93.98 0.00 98.62 0.00 93.33 0.00 97.19 0.02 95.45 0.00 99.26 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_mailbox.3680198403
96.60 0.01 98.38 0.00 93.99 0.01 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 99.26 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_errors.643661665

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.1021305903
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1634144237
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.4195149766
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.4292893942
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.2969132724
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.3201051664
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.634722969
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.990749277
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.3991028059
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.740943897
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1165102152
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3333055544
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.516987058
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.2665079458
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.1737261951
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.4279409767
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.2648165938
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1139688222
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.1656722259
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.4047914105
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_rw.1593919575
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_intr_test.1911789755
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1349067794
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_intg_err.3522812677
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3349620299
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_rw.2552002378
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_intr_test.1882149280
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.727533164
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_intg_err.3832153149
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3983912662
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/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_all.1528767162
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_read_hw_reg.3246598459
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_rw.3414460558
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_sts_read.4066971323
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_upload.2127173565
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_alert_test.2388434099
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_cfg_cmd.730367421
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_csb_read.3331829872
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_all.3750111019
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_and_tpm.2965458465
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_and_tpm_min_idle.1406580232
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_mode.1875053748
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_mode_ignore_cmds.195659110
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_intercept.3670106227
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/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_upload.1671684052
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_alert_test.2638939702
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_cfg_cmd.1306967559
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_csb_read.2154408290
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_all.4090093092
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_and_tpm.1583165511
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_and_tpm_min_idle.750005926
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_mode.3339501308
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_mode_ignore_cmds.2882854580
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_intercept.858392736
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_mailbox.1811114761
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.3288257222
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_pass_cmd_filtering.1283529847
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_read_buffer_direct.574756775
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_stress_all.2348335628
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_all.2005021052
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_read_hw_reg.1241837078
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_rw.2838262804
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_sts_read.2164864946
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/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_alert_test.3944846122
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_cfg_cmd.2291287304
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_csb_read.4036422934
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_all.162055317
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_and_tpm.3491612236
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_and_tpm_min_idle.408539842
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_mode.3571846522
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.10326557
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_intercept.251912572
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_mailbox.2260016798
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/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_pass_cmd_filtering.2965180537
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/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_and_tpm.891893860
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_and_tpm_min_idle.125226379
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_mode.796343
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_mode_ignore_cmds.530683795
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_intercept.292202324
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_mailbox.3119090320
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.1548302027
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.971814378
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.388643257
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_stress_all.1111446854
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_all.1084146595
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.2737855394
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_rw.665777169
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.264758
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_upload.2765345397



Total test records in report: 1131
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_csb_read.1904975290 Sep 01 02:45:57 PM UTC 24 Sep 01 02:45:59 PM UTC 24 15380084 ps
T2 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_ram_cfg.1245827071 Sep 01 02:45:58 PM UTC 24 Sep 01 02:46:00 PM UTC 24 20928158 ps
T3 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_rw.2886732662 Sep 01 02:45:58 PM UTC 24 Sep 01 02:46:00 PM UTC 24 75317680 ps
T4 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_sts_read.3654359276 Sep 01 02:45:58 PM UTC 24 Sep 01 02:46:00 PM UTC 24 28637505 ps
T5 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_pass_cmd_filtering.1314876878 Sep 01 02:45:58 PM UTC 24 Sep 01 02:46:03 PM UTC 24 244339261 ps
T6 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_sec_cm.2456451374 Sep 01 02:46:00 PM UTC 24 Sep 01 02:46:03 PM UTC 24 458196741 ps
T7 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_mode.2120769103 Sep 01 02:47:32 PM UTC 24 Sep 01 02:47:41 PM UTC 24 4457947589 ps
T8 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_csb_read.3676789813 Sep 01 02:46:01 PM UTC 24 Sep 01 02:46:03 PM UTC 24 15788647 ps
T9 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_alert_test.2951614903 Sep 01 02:46:01 PM UTC 24 Sep 01 02:46:03 PM UTC 24 15326779 ps
T10 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_upload.296832309 Sep 01 02:46:00 PM UTC 24 Sep 01 02:46:06 PM UTC 24 973286109 ps
T11 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_sts_read.1632077127 Sep 01 02:46:03 PM UTC 24 Sep 01 02:46:06 PM UTC 24 115292754 ps
T12 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_rw.1520639893 Sep 01 02:46:03 PM UTC 24 Sep 01 02:46:06 PM UTC 24 93569040 ps
T13 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_all.3535898173 Sep 01 02:45:58 PM UTC 24 Sep 01 02:46:10 PM UTC 24 2698729120 ps
T24 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_cfg_cmd.1222252922 Sep 01 02:46:07 PM UTC 24 Sep 01 02:46:11 PM UTC 24 420683279 ps
T14 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_pass_addr_payload_swap.2480704795 Sep 01 02:46:05 PM UTC 24 Sep 01 02:46:12 PM UTC 24 2512430475 ps
T15 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_mode.2244175579 Sep 01 02:46:07 PM UTC 24 Sep 01 02:46:14 PM UTC 24 638708976 ps
T16 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_read_buffer_direct.4255317355 Sep 01 02:46:00 PM UTC 24 Sep 01 02:46:15 PM UTC 24 3581107445 ps
T25 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_read_hw_reg.3353224194 Sep 01 02:45:58 PM UTC 24 Sep 01 02:46:15 PM UTC 24 1856291276 ps
T17 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_cfg_cmd.3265987675 Sep 01 02:46:00 PM UTC 24 Sep 01 02:46:15 PM UTC 24 4224249393 ps
T26 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_read_hw_reg.1933834933 Sep 01 02:46:01 PM UTC 24 Sep 01 02:46:16 PM UTC 24 2401125100 ps
T18 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_intercept.1850168433 Sep 01 02:45:58 PM UTC 24 Sep 01 02:46:17 PM UTC 24 3695305579 ps
T19 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_pass_cmd_filtering.1865190869 Sep 01 02:46:03 PM UTC 24 Sep 01 02:46:17 PM UTC 24 6442834911 ps
T20 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_intercept.583680337 Sep 01 02:46:05 PM UTC 24 Sep 01 02:46:17 PM UTC 24 3571911228 ps
T98 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_alert_test.1853393688 Sep 01 02:46:16 PM UTC 24 Sep 01 02:46:18 PM UTC 24 136410684 ps
T27 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_csb_read.1800636201 Sep 01 02:46:16 PM UTC 24 Sep 01 02:46:19 PM UTC 24 110660958 ps
T53 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_upload.990822018 Sep 01 02:46:07 PM UTC 24 Sep 01 02:46:19 PM UTC 24 973633034 ps
T21 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_sec_cm.2470470591 Sep 01 02:46:16 PM UTC 24 Sep 01 02:46:19 PM UTC 24 182000214 ps
T39 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_read_buffer_direct.2658048131 Sep 01 02:46:12 PM UTC 24 Sep 01 02:46:21 PM UTC 24 783425872 ps
T28 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_sts_read.3724847124 Sep 01 02:46:20 PM UTC 24 Sep 01 02:46:22 PM UTC 24 24040477 ps
T29 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_rw.3387477248 Sep 01 02:46:20 PM UTC 24 Sep 01 02:46:23 PM UTC 24 51375307 ps
T54 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_mailbox.2097236427 Sep 01 02:45:59 PM UTC 24 Sep 01 02:46:28 PM UTC 24 6785554086 ps
T64 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_cfg_cmd.2985177595 Sep 01 02:46:23 PM UTC 24 Sep 01 02:46:29 PM UTC 24 1413128255 ps
T59 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_upload.1966662278 Sep 01 02:46:23 PM UTC 24 Sep 01 02:46:34 PM UTC 24 609460515 ps
T60 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_pass_addr_payload_swap.2997232745 Sep 01 02:45:58 PM UTC 24 Sep 01 02:46:36 PM UTC 24 12778178509 ps
T52 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_mode.3457397831 Sep 01 02:46:28 PM UTC 24 Sep 01 02:46:37 PM UTC 24 196080804 ps
T30 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_read_hw_reg.1847664373 Sep 01 02:46:18 PM UTC 24 Sep 01 02:46:37 PM UTC 24 3271483282 ps
T22 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_sec_cm.2881040473 Sep 01 02:46:38 PM UTC 24 Sep 01 02:46:40 PM UTC 24 195497494 ps
T56 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_mailbox.2671959272 Sep 01 02:46:22 PM UTC 24 Sep 01 02:46:43 PM UTC 24 460034462 ps
T99 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_alert_test.1305714329 Sep 01 02:46:41 PM UTC 24 Sep 01 02:46:43 PM UTC 24 14660670 ps
T165 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_mode.306394332 Sep 01 02:46:00 PM UTC 24 Sep 01 02:46:43 PM UTC 24 2360001142 ps
T396 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_csb_read.4004733911 Sep 01 02:46:43 PM UTC 24 Sep 01 02:46:45 PM UTC 24 22824190 ps
T61 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_pass_cmd_filtering.555620001 Sep 01 02:46:20 PM UTC 24 Sep 01 02:46:48 PM UTC 24 74882222948 ps
T58 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_pass_addr_payload_swap.468698208 Sep 01 02:46:20 PM UTC 24 Sep 01 02:46:48 PM UTC 24 8269295583 ps
T114 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_mailbox.3680198403 Sep 01 02:46:05 PM UTC 24 Sep 01 02:46:49 PM UTC 24 4195009579 ps
T31 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_sts_read.1927605997 Sep 01 02:46:47 PM UTC 24 Sep 01 02:46:50 PM UTC 24 52300964 ps
T32 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_rw.3760966183 Sep 01 02:46:48 PM UTC 24 Sep 01 02:46:51 PM UTC 24 111011633 ps
T43 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_all.826271237 Sep 01 02:46:02 PM UTC 24 Sep 01 02:46:54 PM UTC 24 25243634260 ps
T97 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_read_buffer_direct.4109385815 Sep 01 02:46:31 PM UTC 24 Sep 01 02:46:54 PM UTC 24 11504690942 ps
T120 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_cfg_cmd.987147916 Sep 01 02:46:55 PM UTC 24 Sep 01 02:46:59 PM UTC 24 32078888 ps
T44 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_mode_ignore_cmds.4168563257 Sep 01 02:46:11 PM UTC 24 Sep 01 02:47:00 PM UTC 24 1603153610 ps
T55 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_pass_addr_payload_swap.2834133060 Sep 01 02:46:50 PM UTC 24 Sep 01 02:47:01 PM UTC 24 2476797954 ps
T47 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_all.1179353078 Sep 01 02:46:18 PM UTC 24 Sep 01 02:47:02 PM UTC 24 35918092189 ps
T57 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_intercept.3466492069 Sep 01 02:46:51 PM UTC 24 Sep 01 02:47:02 PM UTC 24 507190228 ps
T75 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_upload.2250452463 Sep 01 02:46:55 PM UTC 24 Sep 01 02:47:08 PM UTC 24 1833888998 ps
T76 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_read_hw_reg.3923564620 Sep 01 02:46:44 PM UTC 24 Sep 01 02:47:08 PM UTC 24 14284628688 ps
T23 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_sec_cm.1922904573 Sep 01 02:47:11 PM UTC 24 Sep 01 02:47:13 PM UTC 24 164507601 ps
T77 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_read_buffer_direct.2938298917 Sep 01 02:47:01 PM UTC 24 Sep 01 02:47:15 PM UTC 24 4272635436 ps
T78 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_mode.2267533537 Sep 01 02:47:00 PM UTC 24 Sep 01 02:47:16 PM UTC 24 790887876 ps
T103 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_alert_test.3817143423 Sep 01 02:47:15 PM UTC 24 Sep 01 02:47:17 PM UTC 24 13464413 ps
T94 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_pass_cmd_filtering.3998203626 Sep 01 02:46:50 PM UTC 24 Sep 01 02:47:18 PM UTC 24 6503931939 ps
T95 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_cfg_cmd.2635672350 Sep 01 02:47:30 PM UTC 24 Sep 01 02:47:43 PM UTC 24 2621800179 ps
T397 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_csb_read.1778452386 Sep 01 02:47:17 PM UTC 24 Sep 01 02:47:19 PM UTC 24 32372196 ps
T398 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_sts_read.3752068437 Sep 01 02:47:20 PM UTC 24 Sep 01 02:47:23 PM UTC 24 33166856 ps
T45 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_rw.1121949030 Sep 01 02:47:20 PM UTC 24 Sep 01 02:47:23 PM UTC 24 36690751 ps
T399 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_alert_test.3001927002 Sep 01 02:47:37 PM UTC 24 Sep 01 02:47:40 PM UTC 24 15163234 ps
T48 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_and_tpm_min_idle.2090953992 Sep 01 02:46:37 PM UTC 24 Sep 01 02:47:26 PM UTC 24 6005348586 ps
T49 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_and_tpm_min_idle.1450363895 Sep 01 02:46:15 PM UTC 24 Sep 01 02:47:26 PM UTC 24 3218750995 ps
T121 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_pass_addr_payload_swap.295220056 Sep 01 02:47:24 PM UTC 24 Sep 01 02:47:29 PM UTC 24 1150345065 ps
T96 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_all.2187097595 Sep 01 02:46:46 PM UTC 24 Sep 01 02:47:29 PM UTC 24 9943356263 ps
T51 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_all.709702675 Sep 01 02:46:00 PM UTC 24 Sep 01 02:47:31 PM UTC 24 24295235049 ps
T62 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_and_tpm.3772694709 Sep 01 02:47:02 PM UTC 24 Sep 01 02:47:32 PM UTC 24 6775345564 ps
T207 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_intercept.4028587929 Sep 01 02:46:21 PM UTC 24 Sep 01 02:47:33 PM UTC 24 9071433825 ps
T283 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_mailbox.3774168318 Sep 01 02:47:27 PM UTC 24 Sep 01 02:47:34 PM UTC 24 1043690279 ps
T198 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_pass_cmd_filtering.165215762 Sep 01 02:47:24 PM UTC 24 Sep 01 02:47:34 PM UTC 24 965247858 ps
T122 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_mailbox.736893465 Sep 01 02:46:52 PM UTC 24 Sep 01 02:47:34 PM UTC 24 5619677284 ps
T113 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_intercept.3866005799 Sep 01 02:47:27 PM UTC 24 Sep 01 02:47:37 PM UTC 24 369698344 ps
T33 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_sec_cm.2198710553 Sep 01 02:47:35 PM UTC 24 Sep 01 02:47:38 PM UTC 24 96673741 ps
T400 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_csb_read.1810163189 Sep 01 02:47:38 PM UTC 24 Sep 01 02:47:41 PM UTC 24 23040408 ps
T34 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_stress_all.1876364407 Sep 01 02:46:38 PM UTC 24 Sep 01 02:47:44 PM UTC 24 5833541957 ps
T401 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_sts_read.4066971323 Sep 01 02:47:42 PM UTC 24 Sep 01 02:47:44 PM UTC 24 36683649 ps
T63 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_mode_ignore_cmds.662863083 Sep 01 02:46:30 PM UTC 24 Sep 01 02:47:45 PM UTC 24 2705441678 ps
T389 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_rw.3414460558 Sep 01 02:47:43 PM UTC 24 Sep 01 02:47:45 PM UTC 24 19542987 ps
T402 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_read_hw_reg.1781634448 Sep 01 02:47:18 PM UTC 24 Sep 01 02:47:46 PM UTC 24 22834443361 ps
T403 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_read_hw_reg.3246598459 Sep 01 02:47:41 PM UTC 24 Sep 01 02:47:47 PM UTC 24 341045321 ps
T166 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_read_buffer_direct.2886403409 Sep 01 02:47:33 PM UTC 24 Sep 01 02:47:47 PM UTC 24 9959458435 ps
T404 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_mode_ignore_cmds.496442120 Sep 01 02:47:48 PM UTC 24 Sep 01 02:47:51 PM UTC 24 33430951 ps
T405 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_mode.3555674800 Sep 01 02:47:48 PM UTC 24 Sep 01 02:47:53 PM UTC 24 123893713 ps
T279 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_pass_addr_payload_swap.96738184 Sep 01 02:47:45 PM UTC 24 Sep 01 02:47:53 PM UTC 24 6726492728 ps
T258 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_upload.2127173565 Sep 01 02:47:46 PM UTC 24 Sep 01 02:47:53 PM UTC 24 158357776 ps
T69 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_and_tpm.3579009615 Sep 01 02:46:00 PM UTC 24 Sep 01 02:47:56 PM UTC 24 42088193380 ps
T65 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_upload.429531845 Sep 01 02:47:30 PM UTC 24 Sep 01 02:47:58 PM UTC 24 3333872189 ps
T110 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_cfg_cmd.3296293442 Sep 01 02:47:47 PM UTC 24 Sep 01 02:47:59 PM UTC 24 384682586 ps
T167 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_read_buffer_direct.3815170452 Sep 01 02:47:52 PM UTC 24 Sep 01 02:48:00 PM UTC 24 269342648 ps
T406 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_alert_test.1965654398 Sep 01 02:47:59 PM UTC 24 Sep 01 02:48:01 PM UTC 24 31262413 ps
T67 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_pass_cmd_filtering.1329451181 Sep 01 02:47:44 PM UTC 24 Sep 01 02:48:02 PM UTC 24 662674665 ps
T407 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_csb_read.3331829872 Sep 01 02:48:00 PM UTC 24 Sep 01 02:48:02 PM UTC 24 17040364 ps
T46 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_all.2701574685 Sep 01 02:47:54 PM UTC 24 Sep 01 02:48:05 PM UTC 24 294256095 ps
T408 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_sts_read.47005427 Sep 01 02:48:03 PM UTC 24 Sep 01 02:48:06 PM UTC 24 157355146 ps
T386 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_rw.1150625744 Sep 01 02:48:04 PM UTC 24 Sep 01 02:48:11 PM UTC 24 1139969429 ps
T92 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_all.2795094684 Sep 01 02:47:02 PM UTC 24 Sep 01 02:48:14 PM UTC 24 18277504910 ps
T409 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_read_hw_reg.1789655780 Sep 01 02:48:02 PM UTC 24 Sep 01 02:48:15 PM UTC 24 6832592522 ps
T123 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_all.3725025620 Sep 01 02:47:19 PM UTC 24 Sep 01 02:48:16 PM UTC 24 39006359729 ps
T267 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_pass_addr_payload_swap.779004859 Sep 01 02:48:07 PM UTC 24 Sep 01 02:48:17 PM UTC 24 417457287 ps
T383 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_all.786949884 Sep 01 02:48:02 PM UTC 24 Sep 01 02:48:19 PM UTC 24 4941498260 ps
T66 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_upload.1671684052 Sep 01 02:48:16 PM UTC 24 Sep 01 02:48:21 PM UTC 24 118877555 ps
T382 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_all.1528767162 Sep 01 02:47:42 PM UTC 24 Sep 01 02:48:22 PM UTC 24 4411385795 ps
T249 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_mailbox.2648386200 Sep 01 02:47:46 PM UTC 24 Sep 01 02:48:23 PM UTC 24 3185889308 ps
T284 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_cfg_cmd.730367421 Sep 01 02:48:17 PM UTC 24 Sep 01 02:48:23 PM UTC 24 946974188 ps
T255 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_intercept.3652412778 Sep 01 02:47:45 PM UTC 24 Sep 01 02:48:24 PM UTC 24 5267036483 ps
T410 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_all.3750111019 Sep 01 02:48:23 PM UTC 24 Sep 01 02:48:25 PM UTC 24 17036575 ps
T93 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_all.3898539411 Sep 01 02:46:12 PM UTC 24 Sep 01 02:48:26 PM UTC 24 41596704324 ps
T234 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_intercept.3670106227 Sep 01 02:48:12 PM UTC 24 Sep 01 02:48:27 PM UTC 24 1060414078 ps
T411 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_alert_test.2388434099 Sep 01 02:48:27 PM UTC 24 Sep 01 02:48:29 PM UTC 24 12511744 ps
T412 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_csb_read.2154408290 Sep 01 02:48:27 PM UTC 24 Sep 01 02:48:29 PM UTC 24 12195438 ps
T70 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_all.2673313116 Sep 01 02:47:34 PM UTC 24 Sep 01 02:48:29 PM UTC 24 1469775731 ps
T273 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_mailbox.3119090320 Sep 01 02:49:55 PM UTC 24 Sep 01 02:50:02 PM UTC 24 439741031 ps
T168 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_read_buffer_direct.3877790670 Sep 01 02:48:22 PM UTC 24 Sep 01 02:48:31 PM UTC 24 1900349663 ps
T413 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_sts_read.2164864946 Sep 01 02:48:30 PM UTC 24 Sep 01 02:48:33 PM UTC 24 87587136 ps
T276 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_mode.1875053748 Sep 01 02:48:18 PM UTC 24 Sep 01 02:48:33 PM UTC 24 463197561 ps
T68 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_pass_cmd_filtering.1587966062 Sep 01 02:48:06 PM UTC 24 Sep 01 02:48:34 PM UTC 24 16196350178 ps
T392 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_rw.2838262804 Sep 01 02:48:31 PM UTC 24 Sep 01 02:48:34 PM UTC 24 99233540 ps
T250 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_pass_cmd_filtering.1283529847 Sep 01 02:48:32 PM UTC 24 Sep 01 02:48:46 PM UTC 24 1060596805 ps
T246 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.3288257222 Sep 01 02:48:33 PM UTC 24 Sep 01 02:48:46 PM UTC 24 998124615 ps
T414 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_read_hw_reg.1241837078 Sep 01 02:48:30 PM UTC 24 Sep 01 02:48:46 PM UTC 24 2405515823 ps
T415 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_mode.3339501308 Sep 01 02:48:47 PM UTC 24 Sep 01 02:48:52 PM UTC 24 98042204 ps
T261 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_intercept.858392736 Sep 01 02:48:34 PM UTC 24 Sep 01 02:48:53 PM UTC 24 9191865382 ps
T169 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_read_buffer_direct.574756775 Sep 01 02:48:50 PM UTC 24 Sep 01 02:48:58 PM UTC 24 355602114 ps
T416 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_cfg_cmd.1306967559 Sep 01 02:48:47 PM UTC 24 Sep 01 02:49:00 PM UTC 24 1390264896 ps
T230 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_upload.578048722 Sep 01 02:48:34 PM UTC 24 Sep 01 02:49:01 PM UTC 24 10819920312 ps
T111 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_mailbox.1811114761 Sep 01 02:48:34 PM UTC 24 Sep 01 02:49:03 PM UTC 24 3617916300 ps
T417 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_alert_test.2638939702 Sep 01 02:49:01 PM UTC 24 Sep 01 02:49:03 PM UTC 24 11961398 ps
T418 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_csb_read.4036422934 Sep 01 02:49:01 PM UTC 24 Sep 01 02:49:04 PM UTC 24 16767599 ps
T419 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_sts_read.2265758492 Sep 01 02:49:05 PM UTC 24 Sep 01 02:49:07 PM UTC 24 93384351 ps
T420 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_rw.2892930337 Sep 01 02:49:07 PM UTC 24 Sep 01 02:49:09 PM UTC 24 166084919 ps
T421 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_read_hw_reg.1420886100 Sep 01 02:49:04 PM UTC 24 Sep 01 02:49:11 PM UTC 24 1119632302 ps
T315 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_pass_cmd_filtering.2965180537 Sep 01 02:49:08 PM UTC 24 Sep 01 02:49:15 PM UTC 24 1520241555 ps
T297 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_mailbox.2260016798 Sep 01 02:49:16 PM UTC 24 Sep 01 02:49:21 PM UTC 24 163906065 ps
T390 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_all.421842005 Sep 01 02:49:05 PM UTC 24 Sep 01 02:49:26 PM UTC 24 2976604064 ps
T71 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_pass_addr_payload_swap.1538809704 Sep 01 02:49:10 PM UTC 24 Sep 01 02:49:29 PM UTC 24 8259376695 ps
T72 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_and_tpm.4217204166 Sep 01 02:47:54 PM UTC 24 Sep 01 02:49:30 PM UTC 24 4305864779 ps
T302 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_intercept.251912572 Sep 01 02:49:12 PM UTC 24 Sep 01 02:49:32 PM UTC 24 1195278436 ps
T422 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_all.162055317 Sep 01 02:49:33 PM UTC 24 Sep 01 02:49:35 PM UTC 24 12782269 ps
T285 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_cfg_cmd.2291287304 Sep 01 02:49:25 PM UTC 24 Sep 01 02:49:36 PM UTC 24 518184398 ps
T313 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_mailbox.687918888 Sep 01 02:48:15 PM UTC 24 Sep 01 02:49:39 PM UTC 24 45327008359 ps
T423 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_alert_test.3944846122 Sep 01 02:49:40 PM UTC 24 Sep 01 02:49:42 PM UTC 24 21886154 ps
T424 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_read_buffer_direct.301330 Sep 01 02:49:31 PM UTC 24 Sep 01 02:49:43 PM UTC 24 444459308 ps
T385 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_all.2005021052 Sep 01 02:48:30 PM UTC 24 Sep 01 02:49:44 PM UTC 24 15995739007 ps
T425 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_csb_read.144339490 Sep 01 02:49:43 PM UTC 24 Sep 01 02:49:45 PM UTC 24 37972503 ps
T426 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.264758 Sep 01 02:49:47 PM UTC 24 Sep 01 02:49:50 PM UTC 24 39547493 ps
T427 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.2737855394 Sep 01 02:49:45 PM UTC 24 Sep 01 02:49:50 PM UTC 24 455696964 ps
T298 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_upload.1349209981 Sep 01 02:49:21 PM UTC 24 Sep 01 02:49:52 PM UTC 24 4428737104 ps
T393 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_rw.665777169 Sep 01 02:49:51 PM UTC 24 Sep 01 02:49:54 PM UTC 24 97718304 ps
T115 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_mode_ignore_cmds.2882854580 Sep 01 02:48:48 PM UTC 24 Sep 01 02:49:57 PM UTC 24 4025636607 ps
T206 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.10326557 Sep 01 02:49:30 PM UTC 24 Sep 01 02:49:57 PM UTC 24 1786639742 ps
T35 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_stress_all.4128506389 Sep 01 02:49:37 PM UTC 24 Sep 01 02:49:57 PM UTC 24 3107293383 ps
T293 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.971814378 Sep 01 02:49:51 PM UTC 24 Sep 01 02:49:59 PM UTC 24 215779049 ps
T203 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_mode_ignore_cmds.2544006928 Sep 01 02:47:00 PM UTC 24 Sep 01 02:50:01 PM UTC 24 13441115505 ps
T316 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_upload.2765345397 Sep 01 02:49:58 PM UTC 24 Sep 01 02:50:04 PM UTC 24 630225813 ps
T300 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_cfg_cmd.1237856135 Sep 01 02:49:58 PM UTC 24 Sep 01 02:50:05 PM UTC 24 169848986 ps
T237 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_intercept.292202324 Sep 01 02:49:55 PM UTC 24 Sep 01 02:50:09 PM UTC 24 1986618164 ps
T428 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.388643257 Sep 01 02:50:01 PM UTC 24 Sep 01 02:50:12 PM UTC 24 1615311929 ps
T73 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.1548302027 Sep 01 02:49:53 PM UTC 24 Sep 01 02:50:12 PM UTC 24 4000758958 ps
T429 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_alert_test.3621975031 Sep 01 02:50:13 PM UTC 24 Sep 01 02:50:15 PM UTC 24 51143298 ps
T430 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_csb_read.2124545056 Sep 01 02:50:13 PM UTC 24 Sep 01 02:50:15 PM UTC 24 16304653 ps
T280 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_mode.796343 Sep 01 02:49:58 PM UTC 24 Sep 01 02:50:15 PM UTC 24 1245663652 ps
T275 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_mode.3571846522 Sep 01 02:49:27 PM UTC 24 Sep 01 02:50:16 PM UTC 24 2686178548 ps
T431 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_alert_test.3719942952 Sep 01 02:52:03 PM UTC 24 Sep 01 02:52:05 PM UTC 24 40349812 ps
T216 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_mode_ignore_cmds.3460845630 Sep 01 02:46:00 PM UTC 24 Sep 01 02:50:19 PM UTC 24 28830214524 ps
T432 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_sts_read.1406412346 Sep 01 02:50:17 PM UTC 24 Sep 01 02:50:19 PM UTC 24 138481008 ps
T50 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_and_tpm.1583165511 Sep 01 02:48:53 PM UTC 24 Sep 01 02:50:21 PM UTC 24 4974269135 ps
T433 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_rw.128616009 Sep 01 02:50:19 PM UTC 24 Sep 01 02:50:21 PM UTC 24 31405881 ps
T434 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_read_hw_reg.4248992604 Sep 01 02:50:16 PM UTC 24 Sep 01 02:50:23 PM UTC 24 1610772214 ps
T204 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_all.2290748625 Sep 01 02:50:03 PM UTC 24 Sep 01 02:50:24 PM UTC 24 5113611697 ps
T435 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_pass_addr_payload_swap.4082682185 Sep 01 02:50:20 PM UTC 24 Sep 01 02:50:25 PM UTC 24 411846756 ps
T301 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_mailbox.3804927026 Sep 01 02:50:22 PM UTC 24 Sep 01 02:50:27 PM UTC 24 37026657 ps
T384 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_all.3957342403 Sep 01 02:50:16 PM UTC 24 Sep 01 02:50:31 PM UTC 24 909015599 ps
T36 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_stress_all.2188472031 Sep 01 02:46:00 PM UTC 24 Sep 01 02:50:33 PM UTC 24 61439424220 ps
T304 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_pass_cmd_filtering.1685152668 Sep 01 02:50:20 PM UTC 24 Sep 01 02:50:35 PM UTC 24 10176643120 ps
T74 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_all.4090093092 Sep 01 02:48:52 PM UTC 24 Sep 01 02:50:37 PM UTC 24 23809536662 ps
T436 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_read_buffer_direct.1715810125 Sep 01 02:50:29 PM UTC 24 Sep 01 02:50:39 PM UTC 24 472651012 ps
T287 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_intercept.1159185219 Sep 01 02:50:21 PM UTC 24 Sep 01 02:50:41 PM UTC 24 3875941775 ps
T437 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_alert_test.2163912187 Sep 01 02:50:40 PM UTC 24 Sep 01 02:50:43 PM UTC 24 14000522 ps
T438 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_csb_read.542685343 Sep 01 02:50:42 PM UTC 24 Sep 01 02:50:45 PM UTC 24 26951503 ps
T439 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_mode.445197651 Sep 01 02:50:26 PM UTC 24 Sep 01 02:50:45 PM UTC 24 657228129 ps
T440 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_sts_read.2148389667 Sep 01 02:50:47 PM UTC 24 Sep 01 02:50:50 PM UTC 24 111525115 ps
T291 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_and_tpm.3491612236 Sep 01 02:49:33 PM UTC 24 Sep 01 02:50:52 PM UTC 24 18261811860 ps
T441 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_rw.4172839456 Sep 01 02:50:50 PM UTC 24 Sep 01 02:50:53 PM UTC 24 107255571 ps
T205 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_mode_ignore_cmds.530683795 Sep 01 02:49:59 PM UTC 24 Sep 01 02:50:56 PM UTC 24 2606604459 ps
T442 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_read_hw_reg.363685322 Sep 01 02:50:46 PM UTC 24 Sep 01 02:50:58 PM UTC 24 1597308306 ps
T443 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_intercept.990857242 Sep 01 02:50:54 PM UTC 24 Sep 01 02:50:59 PM UTC 24 102719564 ps
T387 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_all.1084146595 Sep 01 02:49:46 PM UTC 24 Sep 01 02:50:59 PM UTC 24 34159978017 ps
T444 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_cfg_cmd.3075449707 Sep 01 02:50:25 PM UTC 24 Sep 01 02:50:59 PM UTC 24 7565412384 ps
T309 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_and_tpm_min_idle.750005926 Sep 01 02:48:54 PM UTC 24 Sep 01 02:51:00 PM UTC 24 49831383856 ps
T253 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_pass_cmd_filtering.3712940294 Sep 01 02:50:52 PM UTC 24 Sep 01 02:51:03 PM UTC 24 368221254 ps
T334 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_upload.3201464625 Sep 01 02:51:00 PM UTC 24 Sep 01 02:51:04 PM UTC 24 38839722 ps
T312 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_upload.370039158 Sep 01 02:50:25 PM UTC 24 Sep 01 02:51:04 PM UTC 24 6101634345 ps
T308 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_cfg_cmd.1133756501 Sep 01 02:51:00 PM UTC 24 Sep 01 02:51:08 PM UTC 24 2032374651 ps
T199 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_mode_ignore_cmds.195659110 Sep 01 02:48:20 PM UTC 24 Sep 01 02:51:08 PM UTC 24 63547766386 ps
T445 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_read_buffer_direct.573610775 Sep 01 02:51:01 PM UTC 24 Sep 01 02:51:08 PM UTC 24 100780237 ps
T446 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_and_tpm_min_idle.1569895325 Sep 01 02:50:36 PM UTC 24 Sep 01 02:51:09 PM UTC 24 888997931 ps
T447 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_alert_test.2280417296 Sep 01 02:51:08 PM UTC 24 Sep 01 02:51:10 PM UTC 24 13076023 ps
T311 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_intercept.2109245107 Sep 01 02:51:47 PM UTC 24 Sep 01 02:52:02 PM UTC 24 3248374637 ps
T448 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_csb_read.2787060308 Sep 01 02:51:09 PM UTC 24 Sep 01 02:51:11 PM UTC 24 62256972 ps
T449 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_rw.2897937634 Sep 01 02:51:13 PM UTC 24 Sep 01 02:51:15 PM UTC 24 22180414 ps
T450 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_sts_read.2956365118 Sep 01 02:51:13 PM UTC 24 Sep 01 02:51:15 PM UTC 24 99469183 ps
T326 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_pass_addr_payload_swap.627758261 Sep 01 02:50:54 PM UTC 24 Sep 01 02:51:16 PM UTC 24 3273317122 ps
T370 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_mode.1848624409 Sep 01 02:51:00 PM UTC 24 Sep 01 02:51:20 PM UTC 24 3979924133 ps
T388 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_all.943399112 Sep 01 02:50:46 PM UTC 24 Sep 01 02:51:20 PM UTC 24 1790669694 ps
T451 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_read_hw_reg.1116302609 Sep 01 02:51:10 PM UTC 24 Sep 01 02:51:23 PM UTC 24 2344232831 ps
T324 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_pass_addr_payload_swap.254721012 Sep 01 02:51:16 PM UTC 24 Sep 01 02:51:27 PM UTC 24 2356855514 ps
T104 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_and_tpm_min_idle.408539842 Sep 01 02:49:36 PM UTC 24 Sep 01 02:51:27 PM UTC 24 29850077624 ps
T452 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_all.111008393 Sep 01 02:51:12 PM UTC 24 Sep 01 02:51:28 PM UTC 24 6566703622 ps
T257 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_mailbox.2885801940 Sep 01 02:50:57 PM UTC 24 Sep 01 02:51:30 PM UTC 24 3792823451 ps
T238 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_pass_cmd_filtering.3622396589 Sep 01 02:51:16 PM UTC 24 Sep 01 02:51:30 PM UTC 24 17522342231 ps
T112 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_cfg_cmd.2810331611 Sep 01 02:51:23 PM UTC 24 Sep 01 02:51:30 PM UTC 24 868281859 ps
T453 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_mode_ignore_cmds.1511728810 Sep 01 02:51:28 PM UTC 24 Sep 01 02:51:31 PM UTC 24 28968470 ps
T201 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_and_tpm_min_idle.1201641319 Sep 01 02:47:35 PM UTC 24 Sep 01 02:51:34 PM UTC 24 45052015759 ps
T454 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_alert_test.2840159585 Sep 01 02:51:35 PM UTC 24 Sep 01 02:51:37 PM UTC 24 17260642 ps
T235 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_intercept.2242873926 Sep 01 02:51:17 PM UTC 24 Sep 01 02:51:37 PM UTC 24 1406015829 ps
T371 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_mode.763701984 Sep 01 02:51:27 PM UTC 24 Sep 01 02:51:38 PM UTC 24 265959990 ps
T455 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_csb_read.1065697555 Sep 01 02:51:38 PM UTC 24 Sep 01 02:51:40 PM UTC 24 13815122 ps
T456 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_sts_read.3204193857 Sep 01 02:51:41 PM UTC 24 Sep 01 02:51:44 PM UTC 24 204232302 ps
T105 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_and_tpm.891893860 Sep 01 02:50:04 PM UTC 24 Sep 01 02:51:44 PM UTC 24 5821196628 ps
T281 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_and_tpm.1377898641 Sep 01 02:51:05 PM UTC 24 Sep 01 02:51:46 PM UTC 24 5475647733 ps
T200 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_and_tpm.3217678756 Sep 01 02:46:13 PM UTC 24 Sep 01 02:51:46 PM UTC 24 125899474136 ps
T457 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_rw.1927845888 Sep 01 02:51:44 PM UTC 24 Sep 01 02:51:47 PM UTC 24 56769502 ps
T458 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_all.4109533174 Sep 01 02:51:41 PM UTC 24 Sep 01 02:51:48 PM UTC 24 2895030163 ps
T459 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_read_buffer_direct.3279279337 Sep 01 02:51:29 PM UTC 24 Sep 01 02:51:48 PM UTC 24 5348272338 ps
T277 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_mode_ignore_cmds.953230080 Sep 01 02:51:01 PM UTC 24 Sep 01 02:51:50 PM UTC 24 6727518589 ps
T460 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_read_hw_reg.1540286406 Sep 01 02:51:38 PM UTC 24 Sep 01 02:51:52 PM UTC 24 5503003974 ps
T346 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_upload.3350689206 Sep 01 02:51:21 PM UTC 24 Sep 01 02:51:53 PM UTC 24 5779012219 ps
T227 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_all.1680218576 Sep 01 02:50:32 PM UTC 24 Sep 01 02:51:53 PM UTC 24 4909234071 ps
T274 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_pass_addr_payload_swap.2123736097 Sep 01 02:51:47 PM UTC 24 Sep 01 02:51:59 PM UTC 24 2670624578 ps
T461 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_read_buffer_direct.571680234 Sep 01 02:51:53 PM UTC 24 Sep 01 02:52:02 PM UTC 24 648990172 ps
T340 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_pass_cmd_filtering.1569954835 Sep 01 02:51:46 PM UTC 24 Sep 01 02:52:02 PM UTC 24 2225833703 ps
T372 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_mode.3805159177 Sep 01 02:51:50 PM UTC 24 Sep 01 02:52:05 PM UTC 24 805810170 ps
T223 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_upload.3943797371 Sep 01 02:51:49 PM UTC 24 Sep 01 02:52:05 PM UTC 24 1230356736 ps
T462 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_cfg_cmd.620877871 Sep 01 02:51:49 PM UTC 24 Sep 01 02:52:08 PM UTC 24 4191808376 ps
T232 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_mailbox.543698812 Sep 01 02:53:58 PM UTC 24 Sep 01 02:54:16 PM UTC 24 845480664 ps
T463 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_csb_read.1141162705 Sep 01 02:52:06 PM UTC 24 Sep 01 02:52:08 PM UTC 24 16912745 ps
T464 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_sts_read.543034959 Sep 01 02:52:09 PM UTC 24 Sep 01 02:52:12 PM UTC 24 48752223 ps
T202 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_and_tpm_min_idle.3585254292 Sep 01 02:47:54 PM UTC 24 Sep 01 02:52:13 PM UTC 24 29621724976 ps
T391 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_rw.1462653379 Sep 01 02:52:09 PM UTC 24 Sep 01 02:52:14 PM UTC 24 106426206 ps
T465 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_mailbox.2426318287 Sep 01 02:51:21 PM UTC 24 Sep 01 02:52:14 PM UTC 24 4750300747 ps
T259 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_all.3400230322 Sep 01 02:46:35 PM UTC 24 Sep 01 02:52:18 PM UTC 24 36658802345 ps
T466 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_read_hw_reg.1793361614 Sep 01 02:52:07 PM UTC 24 Sep 01 02:52:20 PM UTC 24 2688031313 ps
T306 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_intercept.3814506824 Sep 01 02:52:14 PM UTC 24 Sep 01 02:52:23 PM UTC 24 636922806 ps
T317 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_pass_cmd_filtering.3890741036 Sep 01 02:52:12 PM UTC 24 Sep 01 02:52:25 PM UTC 24 1935974798 ps
T343 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_cfg_cmd.3442115909 Sep 01 02:52:21 PM UTC 24 Sep 01 02:52:26 PM UTC 24 541295460 ps
T236 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_upload.132815627 Sep 01 02:52:19 PM UTC 24 Sep 01 02:52:30 PM UTC 24 1730041868 ps
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