Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	37759	1			T5	4		T14	2		T17	12
auto[SpiFlashAddrCfg]	8062	1			T10	2		T19	2		T54	6
auto[SpiFlashAddr3b]	9716	1			T5	2		T7	3		T18	2
auto[SpiFlashAddr4b]	7852	1			T7	2		T10	2		T15	1

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

36614

1

T5

6

T7

5

T10

4

auto[1]

26775

1

T14

2

T60

12

T58

20

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32940

1

T5

4

T7

2

T10

2

auto[1]

30449

1

T5

2

T7

3

T10

2

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	42576	1			T5	4		T14	2		T17	12
values[1]	1225	1			T53	2		T52	1		T58	2
values[2]	1515	1			T44	1		T75	4		T48	3
values[3]	1487	1			T7	3		T19	2		T20	6
values[4]	1596	1			T19	4		T64	2		T59	2
values[5]	1513	1			T18	8		T61	4		T44	10
values[6]	1581	1			T59	2		T44	4		T49	3
values[7]	1471	1			T54	2		T59	6		T60	4
values[8]	10425	1			T5	2		T7	2		T10	4

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32044

1

T5

6

T10

4

T14

2

auto[1]

31345

1

T7

5

T15

1

T52

3

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

59887

1

T5

4

T7

5

T10

4

write

3502

1

T5

2

T14

2

T44

24

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

20364

1

T5

2

T7

2

T10

4

valids[0x1]

43025

1

T5

4

T7

3

T14

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1704	1			T5	2		T19	2		T44	5
internal_process_ops[0x5a]	1675	1			T18	2		T19	2		T60	2
internal_process_ops[0x05]	22851	1			T53	2		T58	4		T114	6
internal_process_ops[0x35]	1619	1			T19	2		T114	4		T44	11
internal_process_ops[0x15]	1669	1			T19	2		T58	2		T44	9
internal_process_ops[0x03]	1118	1			T20	6		T44	5		T57	2
internal_process_ops[0x0b]	1038	1			T7	3		T53	2		T54	2
internal_process_ops[0x3b]	1126	1			T18	2		T60	4		T56	4
internal_process_ops[0x6b]	1152	1			T5	2		T54	6		T52	1
internal_process_ops[0xbb]	1101	1			T7	2		T10	2		T18	6
internal_process_ops[0xeb]	1146	1			T15	1		T59	2		T52	1

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

61674

1

T5

6

T7

5

T10

4

auto[1]

1715

1

T14

2

T44

16

T55

2

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

60887

1

T5

6

T7

5

T10

4

auto[1]

2502

1

T44

14

T49

8

T51

6

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10920

1

T5

2

T17

12

T19

8

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6517

1

T58

8

T55

12

T48

5

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2184

1

T10

2

T19

2

T54

6

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1953

1

T60

8

T58

8

T55

8

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2616

1

T5

2

T18

2

T19

6

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2283

1

T60

2

T58

4

T55

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2073

1

T10

2

T18

8

T20

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1803

1

T60

2

T48

1

T62

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

140

1

T5

2

T94

2

T198

4

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

92

1

T63

1

T70

1

T72

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

80

1

T70

1

T72

1

T36

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

116

1

T14

2

T63

1

T71

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

116

1

T57

2

T66

2

T72

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

78

1

T63

1

T199

1

T200

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

102

1

T50

1

T36

4

T201

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

93

1

T69

1

T70

1

T74

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

98

1

T48

1

T36

5

T74

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

92

1

T63

2

T36

2

T74

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

108

1

T63

1

T70

1

T36

4

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

106

1

T55

2

T63

5

T73

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

139

1

T63

2

T65

4

T67

4

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

112

1

T201

2

T200

2

T202

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

113

1

T62

6

T63

5

T72

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

110

1

T63

1

T70

1

T36

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11922

1

T52

1

T44

60

T49

76

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7541

1

T44

28

T49

43

T51

8

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1589

1

T52

1

T44

20

T49

15

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1465

1

T44

17

T49

19

T51

7

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1952

1

T7

3

T52

1

T165

5

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1996

1

T44

18

T49

18

T51

11

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1592

1

T7

2

T15

1

T44

12

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1481

1

T44

21

T49

7

T51

5

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

109

1

T44

2

T49

3

T34

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

95

1

T44

3

T49

1

T93

4

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

105

1

T44

1

T49

3

T93

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

122

1

T44

4

T34

2

T93

4

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

126

1

T93

2

T203

1

T204

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

118

1

T44

2

T49

3

T51

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

122

1

T44

1

T93

2

T203

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

116

1

T44

1

T34

2

T93

4

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

110

1

T44

3

T51

1

T34

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

121

1

T44

2

T34

1

T92

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

120

1

T51

1

T93

10

T205

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

114

1

T44

2

T51

2

T93

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

106

1

T49

1

T92

3

T206

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

114

1

T44

2

T51

3

T34

4

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

93

1

T44

1

T46

1

T93

5

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

116

1

T49

1

T92

2

T203

2

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	4042	1			T17	12		T64	8		T61	4
auto[0]	values[0]	valids[0x1]	16310	1			T5	4		T14	2		T18	2
auto[0]	values[1]	valids[0x1]	634	1			T53	2		T58	2		T55	2
auto[0]	values[2]	valids[0x0]	583	1			T48	1		T62	1		T63	10
auto[0]	values[2]	valids[0x1]	283	1			T75	4		T48	2		T70	2
auto[0]	values[3]	valids[0x0]	533	1			T58	4		T48	2		T63	4
auto[0]	values[3]	valids[0x1]	314	1			T19	2		T20	6		T55	12
auto[0]	values[4]	valids[0x0]	555	1			T19	4		T59	2		T207	2
auto[0]	values[4]	valids[0x1]	318	1			T64	2		T94	6		T48	1
auto[0]	values[5]	valids[0x0]	555	1			T18	8		T61	4		T55	4
auto[0]	values[5]	valids[0x1]	329	1			T94	4		T48	2		T70	4
auto[0]	values[6]	valids[0x0]	597	1			T59	2		T62	1		T63	5
auto[0]	values[6]	valids[0x1]	336	1			T207	8		T63	2		T68	2
auto[0]	values[7]	valids[0x0]	499	1			T54	2		T59	2		T60	4
auto[0]	values[7]	valids[0x1]	313	1			T59	4		T58	2		T63	2
auto[0]	values[8]	valids[0x0]	3748	1			T5	2		T10	4		T20	2
auto[0]	values[8]	valids[0x1]	2095	1			T19	4		T53	2		T54	2
auto[1]	values[0]	valids[0x0]	4232	1			T44	48		T49	48		T51	20
auto[1]	values[0]	valids[0x1]	17992	1			T44	79		T49	103		T51	95
auto[1]	values[1]	valids[0x1]	591	1			T52	1		T44	9		T49	2
auto[1]	values[2]	valids[0x0]	373	1			T44	1		T49	10		T51	2
auto[1]	values[2]	valids[0x1]	276	1			T49	2		T51	1		T92	5
auto[1]	values[3]	valids[0x0]	362	1			T44	9		T49	3		T51	1
auto[1]	values[3]	valids[0x1]	278	1			T7	3		T44	4		T49	1
auto[1]	values[4]	valids[0x0]	420	1			T44	6		T49	2		T51	2
auto[1]	values[4]	valids[0x1]	303	1			T44	8		T51	1		T93	4
auto[1]	values[5]	valids[0x0]	379	1			T44	6		T49	1		T51	3
auto[1]	values[5]	valids[0x1]	250	1			T44	4		T49	2		T51	1
auto[1]	values[6]	valids[0x0]	398	1			T44	4		T49	2		T51	6
auto[1]	values[6]	valids[0x1]	250	1			T49	1		T51	1		T92	8
auto[1]	values[7]	valids[0x0]	406	1			T44	6		T51	8		T46	2
auto[1]	values[7]	valids[0x1]	253	1			T44	4		T49	3		T34	2
auto[1]	values[8]	valids[0x0]	2682	1			T7	2		T15	1		T52	1
auto[1]	values[8]	valids[0x1]	1900	1			T52	1		T44	27		T49	12