Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3320252

1

T5

1

T7

448

T10

1

auto[1]

28217

1

T44

958

T49

47

T51

74

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

932846

1

T5

1

T7

448

T10

1

auto[1]

2415623

1

T53

5918

T44

6921

T75

776

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	658243	1			T5	1		T7	2		T10	1
auto[524288:1048575]	411535	1			T7	151		T17	11		T20	8
auto[1048576:1572863]	403418	1			T17	745		T18	3		T64	3
auto[1572864:2097151]	334487	1			T7	199		T17	669		T18	1161
auto[2097152:2621439]	368135	1			T17	645		T18	922		T20	1
auto[2621440:3145727]	406334	1			T17	665		T18	969		T54	2667
auto[3145728:3670015]	392699	1			T7	96		T17	754		T18	918
auto[3670016:4194303]	373618	1			T15	2		T20	301		T54	498

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2449620

1

T5

1

T7

8

T10

1

auto[1]

898849

1

T7

440

T15

175

T17

3353

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2894948

1

T5

1

T7

448

T10

1

auto[1]

453521

1

T17

779

T64

18

T44

1005

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	217544	1			T5	1		T7	2		T10	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	367765	1			T53	5918		T44	388		T75	776
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	104085	1			T7	151		T17	11		T20	8
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	247314	1			T44	256		T49	2276		T122	126
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	82212	1			T17	47		T18	3		T52	249
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	260876	1			T44	10		T49	1974		T34	352
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	76097	1			T7	199		T17	669		T18	1161
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	201578	1			T44	616		T49	1772		T51	3017
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	99891	1			T17	645		T18	922		T20	1
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	216578	1			T44	2		T49	1052		T122	128
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	110989	1			T17	665		T18	969		T54	2667
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	230437	1			T49	3		T207	1		T122	2
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	108576	1			T7	96		T17	673		T18	918
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	225086	1			T44	2716		T49	256		T51	5
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	117507	1			T15	2		T20	301		T54	498
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	205178	1			T44	1192		T48	128		T49	2532
auto[0]	auto[1]	auto[0:524287]	auto[0]	1852	1			T64	15		T95	2		T34	2
auto[0]	auto[1]	auto[0:524287]	auto[1]	66438	1			T34	257		T63	283		T70	256
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	1456	1			T95	568		T51	1		T92	1
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	56110	1			T93	1		T206	564		T203	1044
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	3557	1			T17	698		T64	3		T44	22
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	52950	1			T44	256		T48	260		T63	2877
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	1102	1			T44	34		T93	5		T203	18
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	51743	1			T44	516		T93	646		T36	1962
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	586	1			T44	14		T95	7		T49	2
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	47178	1			T49	261		T34	1		T92	770
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	946	1			T44	12		T51	1		T62	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	60265	1			T34	1		T46	2827		T203	2856
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	1141	1			T17	81		T44	5		T95	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	54908	1			T63	512		T74	512		T104	128
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	1197	1			T44	11		T48	2		T49	3
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	47110	1			T44	128		T49	512		T63	640
auto[1]	auto[0]	auto[0:524287]	auto[0]	498	1			T44	25		T49	1		T34	2
auto[1]	auto[0]	auto[0:524287]	auto[1]	3278	1			T49	3		T34	51		T65	49
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	406	1			T44	10		T49	1		T63	24
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1754	1			T44	128		T49	12		T92	39
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	416	1			T44	12		T49	1		T34	2
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2696	1			T44	1		T49	8		T34	3
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	405	1			T44	23		T49	1		T51	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2826	1			T44	708		T49	5		T51	5
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	425	1			T44	8		T49	2		T34	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2774	1			T44	3		T49	9		T34	4
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	443	1			T44	5		T49	1		T34	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2511	1			T49	1		T34	15		T206	109
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	335	1			T44	15		T51	5		T63	8
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2280	1			T51	63		T92	20		T93	10
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	417	1			T44	12		T49	1		T34	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1771	1			T44	1		T49	1		T34	1
auto[1]	auto[1]	auto[0:524287]	auto[0]	133	1			T44	7		T34	1		T201	3
auto[1]	auto[1]	auto[0:524287]	auto[1]	735	1			T34	1		T201	5		T268	11
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	85	1			T93	1		T203	8		T205	2
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	325	1			T93	49		T227	27		T197	3
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	132	1			T93	1		T36	1		T205	5
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	579	1			T93	16		T36	1		T104	16
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	93	1			T93	2		T74	1		T104	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	643	1			T93	17		T74	34		T104	27
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	83	1			T34	1		T93	1		T50	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	620	1			T34	11		T93	27		T36	7
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	112	1			T34	1		T50	1		T36	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	631	1			T34	4		T50	3		T36	2
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	45	1			T281	1		T282	1		T247	7
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	328	1			T281	8		T282	57		T151	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	80	1			T63	5		T104	1		T105	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	358	1			T104	2		T105	38		T251	2

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1979903	1			T5	1		T7	8		T10	1
auto[0]	auto[0]	auto[1]	891810	1			T7	440		T15	175		T17	2644
auto[0]	auto[1]	auto[0]	442216	1			T17	70		T64	12		T44	998
auto[0]	auto[1]	auto[1]	6323	1			T17	709		T64	6		T95	570
auto[1]	auto[0]	auto[0]	22641	1			T44	946		T49	47		T51	70
auto[1]	auto[0]	auto[1]	594	1			T44	5		T51	4		T63	8
auto[1]	auto[1]	auto[0]	4860	1			T44	6		T34	19		T63	5
auto[1]	auto[1]	auto[1]	122	1			T44	1		T93	2		T203	1