Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	3195844	1			T1	1		T2	1		T3	52
all_pins[1]	3195844	1			T1	1		T2	1		T3	52
all_pins[2]	3195844	1			T1	1		T2	1		T3	52
all_pins[3]	3195844	1			T1	1		T2	1		T3	52
all_pins[4]	3195844	1			T1	1		T2	1		T3	52
all_pins[5]	3195844	1			T1	1		T2	1		T3	52
all_pins[6]	3195844	1			T1	1		T2	1		T3	52
all_pins[7]	3195844	1			T1	1		T2	1		T3	52

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	25379103	1			T1	8		T2	8		T3	416
values[0x1]	187649	1			T34	14		T35	14		T37	5460
transitions[0x0=>0x1]	184973	1			T34	14		T35	10		T37	5134
transitions[0x1=>0x0]	184986	1			T34	14		T35	10		T37	5134

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	3195238	1			T1	1		T2	1		T3	52
all_pins[0]	values[0x1]	606	1			T34	1		T35	1		T37	5
all_pins[0]	transitions[0x0=>0x1]	433	1			T34	1		T35	1		T37	3
all_pins[0]	transitions[0x1=>0x0]	189	1			T34	1		T35	3		T37	1
all_pins[1]	values[0x0]	3195482	1			T1	1		T2	1		T3	52
all_pins[1]	values[0x1]	362	1			T34	1		T35	3		T37	3
all_pins[1]	transitions[0x0=>0x1]	303	1			T34	1		T35	3		T37	2
all_pins[1]	transitions[0x1=>0x0]	262	1			T35	1		T38	57		T196	4
all_pins[2]	values[0x0]	3195523	1			T1	1		T2	1		T3	52
all_pins[2]	values[0x1]	321	1			T35	1		T37	1		T38	59
all_pins[2]	transitions[0x0=>0x1]	280	1			T35	1		T37	1		T38	59
all_pins[2]	transitions[0x1=>0x0]	122	1			T34	3		T35	2		T37	4
all_pins[3]	values[0x0]	3195681	1			T1	1		T2	1		T3	52
all_pins[3]	values[0x1]	163	1			T34	3		T35	2		T37	4
all_pins[3]	transitions[0x0=>0x1]	124	1			T34	3		T35	1		T37	1
all_pins[3]	transitions[0x1=>0x0]	127	1			T34	1		T35	2		T37	2
all_pins[4]	values[0x0]	3195678	1			T1	1		T2	1		T3	52
all_pins[4]	values[0x1]	166	1			T34	1		T35	3		T37	5
all_pins[4]	transitions[0x0=>0x1]	131	1			T34	1		T35	2		T37	5
all_pins[4]	transitions[0x1=>0x0]	2499	1			T34	1		T37	323		T38	170
all_pins[5]	values[0x0]	3193310	1			T1	1		T2	1		T3	52
all_pins[5]	values[0x1]	2534	1			T34	1		T35	1		T37	323
all_pins[5]	transitions[0x0=>0x1]	300	1			T34	1		T37	5		T38	171
all_pins[5]	transitions[0x1=>0x0]	181082	1			T34	2		T35	1		T37	4798
all_pins[6]	values[0x0]	3012528	1			T1	1		T2	1		T3	52
all_pins[6]	values[0x1]	183316	1			T34	2		T35	2		T37	5116
all_pins[6]	transitions[0x0=>0x1]	183264	1			T34	2		T35	1		T37	5114
all_pins[6]	transitions[0x1=>0x0]	129	1			T34	5		T37	1		T38	3
all_pins[7]	values[0x0]	3195663	1			T1	1		T2	1		T3	52
all_pins[7]	values[0x1]	181	1			T34	5		T35	1		T37	3
all_pins[7]	transitions[0x0=>0x1]	138	1			T34	5		T35	1		T37	3
all_pins[7]	transitions[0x1=>0x0]	576	1			T34	1		T35	1		T37	5