Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18660

1

T5

6

T10

4

T17

12

auto[1]

13384

1

T14

2

T60

12

T58

20

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3726	1			T56	6		T75	16		T48	20
values[1]	3994	1			T54	10		T58	20		T198	16
values[2]	3400	1			T55	24		T57	16		T94	16
values[3]	3716	1			T110	14		T234	8		T70	43
values[4]	4018	1			T5	6		T18	10		T114	16
values[5]	5179	1			T17	12		T20	8		T61	18
values[6]	4014	1			T14	2		T19	16		T53	6
values[7]	3997	1			T10	4		T60	12		T122	2

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4537	1			T18	10		T20	8		T53	6
values[1]	3464	1			T5	6		T57	16		T121	4
values[2]	4126	1			T59	16		T114	16		T48	20
values[3]	4457	1			T10	4		T54	10		T56	6
values[4]	3817	1			T19	16		T113	6		T63	60
values[5]	3831	1			T64	10		T94	16		T283	2
values[6]	3840	1			T14	2		T17	12		T48	20
values[7]	3972	1			T60	12		T61	18		T62	20

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	323	1			T258	4		T199	10		T202	13
auto[0]	values[0]	values[1]	305	1			T284	4		T68	22		T36	9
auto[0]	values[0]	values[2]	289	1			T48	10		T40	20		T266	12
auto[0]	values[0]	values[3]	282	1			T56	6		T75	16		T285	6
auto[0]	values[0]	values[4]	380	1			T70	12		T201	12		T202	14
auto[0]	values[0]	values[5]	228	1			T283	2		T72	30		T36	9
auto[0]	values[0]	values[6]	265	1			T278	14		T286	2		T266	16
auto[0]	values[0]	values[7]	145	1			T62	10		T38	39		T244	12
auto[0]	values[1]	values[0]	323	1			T261	14		T287	8		T200	15
auto[0]	values[1]	values[1]	290	1			T50	13		T259	10		T278	23
auto[0]	values[1]	values[2]	159	1			T288	4		T289	16		T290	8
auto[0]	values[1]	values[3]	364	1			T54	10		T277	15		T38	11
auto[0]	values[1]	values[4]	426	1			T113	6		T233	16		T188	11
auto[0]	values[1]	values[5]	192	1			T63	11		T36	13		T38	39
auto[0]	values[1]	values[6]	241	1			T36	17		T291	15		T292	5
auto[0]	values[1]	values[7]	301	1			T198	16		T72	11		T293	4
auto[0]	values[2]	values[0]	304	1			T294	16		T252	9		T295	14
auto[0]	values[2]	values[1]	162	1			T57	16		T69	13		T50	16
auto[0]	values[2]	values[2]	344	1			T269	8		T251	16		T296	4
auto[0]	values[2]	values[3]	182	1			T95	20		T201	10		T179	14
auto[0]	values[2]	values[4]	159	1			T63	15		T297	2		T252	10
auto[0]	values[2]	values[5]	302	1			T94	16		T38	21		T194	19
auto[0]	values[2]	values[6]	283	1			T298	14		T237	20		T194	9
auto[0]	values[2]	values[7]	395	1			T63	18		T66	84		T38	16
auto[0]	values[3]	values[0]	190	1			T40	14		T299	12		T266	18
auto[0]	values[3]	values[1]	235	1			T300	20		T74	10		T224	16
auto[0]	values[3]	values[2]	325	1			T72	11		T257	10		T179	17
auto[0]	values[3]	values[3]	317	1			T36	13		T251	11		T262	8
auto[0]	values[3]	values[4]	260	1			T70	32		T301	2		T74	16
auto[0]	values[3]	values[5]	247	1			T302	10		T199	8		T269	12
auto[0]	values[3]	values[6]	260	1			T110	14		T234	8		T253	26
auto[0]	values[3]	values[7]	218	1			T256	15		T194	10		T303	18
auto[0]	values[4]	values[0]	657	1			T18	10		T63	14		T72	17
auto[0]	values[4]	values[1]	240	1			T5	6		T50	23		T36	7
auto[0]	values[4]	values[2]	241	1			T114	16		T304	6		T201	20
auto[0]	values[4]	values[3]	275	1			T74	13		T202	16		T305	6
auto[0]	values[4]	values[4]	279	1			T63	11		T38	125		T251	12
auto[0]	values[4]	values[5]	353	1			T63	7		T235	20		T194	14
auto[0]	values[4]	values[6]	236	1			T199	4		T306	2		T307	2
auto[0]	values[4]	values[7]	169	1			T251	10		T231	32		T266	9
auto[0]	values[5]	values[0]	289	1			T20	8		T188	11		T40	9
auto[0]	values[5]	values[1]	357	1			T70	10		T200	10		T265	35
auto[0]	values[5]	values[2]	331	1			T201	25		T179	25		T292	31
auto[0]	values[5]	values[3]	523	1			T74	132		T233	12		T254	52
auto[0]	values[5]	values[4]	332	1			T36	32		T201	8		T233	9
auto[0]	values[5]	values[5]	226	1			T67	24		T255	8		T308	10
auto[0]	values[5]	values[6]	461	1			T17	12		T48	13		T201	41
auto[0]	values[5]	values[7]	370	1			T61	18		T36	12		T74	10
auto[0]	values[6]	values[0]	457	1			T53	6		T63	11		T230	56
auto[0]	values[6]	values[1]	156	1			T36	22		T309	22		T310	4
auto[0]	values[6]	values[2]	385	1			T59	16		T201	14		T200	10
auto[0]	values[6]	values[3]	339	1			T311	10		T259	40		T38	12
auto[0]	values[6]	values[4]	172	1			T19	16		T70	11		T312	18
auto[0]	values[6]	values[5]	553	1			T64	10		T65	69		T250	20
auto[0]	values[6]	values[6]	157	1			T256	6		T231	12		T224	8
auto[0]	values[6]	values[7]	215	1			T207	18		T313	10		T199	10
auto[0]	values[7]	values[0]	226	1			T36	17		T74	14		T314	6
auto[0]	values[7]	values[1]	296	1			T122	2		T259	11		T193	67
auto[0]	values[7]	values[2]	314	1			T70	14		T315	2		T201	8
auto[0]	values[7]	values[3]	343	1			T10	4		T249	6		T273	10
auto[0]	values[7]	values[4]	146	1			T63	12		T316	4		T50	16
auto[0]	values[7]	values[5]	288	1			T201	11		T262	12		T278	8
auto[0]	values[7]	values[6]	302	1			T111	4		T259	59		T317	14
auto[0]	values[7]	values[7]	276	1			T72	13		T188	11		T318	6
auto[1]	values[0]	values[0]	174	1			T199	10		T202	10		T188	12
auto[1]	values[0]	values[1]	170	1			T36	11		T201	15		T259	17
auto[1]	values[0]	values[2]	115	1			T48	10		T40	7		T266	14
auto[1]	values[0]	values[3]	155	1			T201	8		T292	3		T319	7
auto[1]	values[0]	values[4]	195	1			T70	8		T201	8		T202	6
auto[1]	values[0]	values[5]	219	1			T72	6		T36	11		T274	16
auto[1]	values[0]	values[6]	258	1			T278	22		T266	7		T181	7
auto[1]	values[0]	values[7]	223	1			T62	10		T38	3		T244	14
auto[1]	values[1]	values[0]	250	1			T58	20		T200	5		T38	14
auto[1]	values[1]	values[1]	219	1			T50	8		T259	10		T278	5
auto[1]	values[1]	values[2]	211	1			T290	12		T80	23		T320	16
auto[1]	values[1]	values[3]	266	1			T277	5		T38	85		T265	7
auto[1]	values[1]	values[4]	203	1			T233	5		T188	23		T278	9
auto[1]	values[1]	values[5]	169	1			T63	9		T36	9		T38	8
auto[1]	values[1]	values[6]	226	1			T36	10		T291	5		T292	19
auto[1]	values[1]	values[7]	154	1			T72	9		T74	5		T202	8
auto[1]	values[2]	values[0]	180	1			T252	11		T321	6		T295	6
auto[1]	values[2]	values[1]	80	1			T69	7		T50	8		T277	10
auto[1]	values[2]	values[2]	243	1			T322	14		T269	12		T251	18
auto[1]	values[2]	values[3]	103	1			T55	24		T201	10		T179	6
auto[1]	values[2]	values[4]	150	1			T63	5		T252	48		T323	8
auto[1]	values[2]	values[5]	188	1			T324	4		T38	6		T194	21
auto[1]	values[2]	values[6]	138	1			T194	15		T325	4		T151	7
auto[1]	values[2]	values[7]	187	1			T63	22		T73	8		T326	10
auto[1]	values[3]	values[0]	233	1			T40	15		T266	5		T327	14
auto[1]	values[3]	values[1]	225	1			T74	50		T224	4		T328	22
auto[1]	values[3]	values[2]	252	1			T72	11		T179	7		T265	81
auto[1]	values[3]	values[3]	143	1			T36	7		T251	9		T262	12
auto[1]	values[3]	values[4]	158	1			T70	11		T74	4		T329	14
auto[1]	values[3]	values[5]	188	1			T199	12		T269	19		T194	6
auto[1]	values[3]	values[6]	149	1			T233	13		T40	8		T247	15
auto[1]	values[3]	values[7]	316	1			T256	5		T194	17		T265	9
auto[1]	values[4]	values[0]	198	1			T63	6		T72	6		T74	12
auto[1]	values[4]	values[1]	184	1			T121	4		T50	11		T36	18
auto[1]	values[4]	values[2]	152	1			T201	6		T224	9		T327	12
auto[1]	values[4]	values[3]	218	1			T74	96		T202	9		T179	11
auto[1]	values[4]	values[4]	242	1			T63	9		T38	23		T251	18
auto[1]	values[4]	values[5]	203	1			T63	13		T194	6		T247	12
auto[1]	values[4]	values[6]	179	1			T199	16		T247	8		T330	10
auto[1]	values[4]	values[7]	192	1			T251	18		T231	13		T266	15
auto[1]	values[5]	values[0]	261	1			T188	9		T40	11		T240	16
auto[1]	values[5]	values[1]	230	1			T70	10		T71	16		T200	16
auto[1]	values[5]	values[2]	252	1			T267	18		T201	15		T179	23
auto[1]	values[5]	values[3]	261	1			T74	32		T233	8		T263	19
auto[1]	values[5]	values[4]	507	1			T36	7		T201	129		T233	11
auto[1]	values[5]	values[5]	127	1			T279	16		T180	11		T331	14
auto[1]	values[5]	values[6]	210	1			T48	7		T201	20		T202	7
auto[1]	values[5]	values[7]	442	1			T36	8		T74	10		T277	9
auto[1]	values[6]	values[0]	324	1			T63	9		T246	4		T36	13
auto[1]	values[6]	values[1]	144	1			T36	18		T309	5		T295	8
auto[1]	values[6]	values[2]	238	1			T201	19		T200	12		T292	31
auto[1]	values[6]	values[3]	228	1			T259	8		T38	8		T265	7
auto[1]	values[6]	values[4]	106	1			T70	21		T200	12		T38	13
auto[1]	values[6]	values[5]	208	1			T201	22		T38	24		T256	6
auto[1]	values[6]	values[6]	149	1			T14	2		T256	14		T231	12
auto[1]	values[6]	values[7]	183	1			T199	10		T231	8		T332	9
auto[1]	values[7]	values[0]	148	1			T36	12		T74	6		T333	10
auto[1]	values[7]	values[1]	171	1			T259	9		T266	7		T180	12
auto[1]	values[7]	values[2]	275	1			T70	6		T201	12		T259	6
auto[1]	values[7]	values[3]	458	1			T74	10		T233	8		T188	29
auto[1]	values[7]	values[4]	102	1			T63	8		T50	9		T231	8
auto[1]	values[7]	values[5]	140	1			T201	9		T262	35		T278	13
auto[1]	values[7]	values[6]	326	1			T259	9		T262	39		T278	21
auto[1]	values[7]	values[7]	186	1			T60	12		T72	8		T188	19