Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

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Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	404	1			T54	6		T56	4		T57	2
auto[ReadAddrCrossIntoMailbox]	277	1			T54	2		T63	3		T70	1
auto[ReadAddrCrossOutOfMailbox]	290	1			T63	1		T70	2		T72	1
auto[ReadAddrCrossAllMailbox]	181	1			T54	2		T56	2		T62	1
auto[ReadAddrOutsideMailbox]	3804	1			T5	2		T10	2		T18	8

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2501

1

T5

1

T10

1

T18

4

auto[1]

2455

1

T5

1

T10

1

T18

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	818	1			T20	6		T121	2		T63	5
read_ops[0x0b]	774	1			T53	2		T54	2		T59	2
read_ops[0x3b]	847	1			T18	2		T60	4		T56	4
read_ops[0x6b]	871	1			T5	2		T54	6		T48	1
read_ops[0xbb]	812	1			T10	2		T18	6		T19	2
read_ops[0xeb]	834	1			T59	2		T56	2		T58	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	23	1			T201	1		T235	1		T277	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	28	1			T36	2		T201	2		T235	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T36	1		T74	1		T335	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	16	1			T36	1		T199	1		T201	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T72	1		T291	1		T256	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T201	1		T233	1		T336	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T36	1		T277	2		T202	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T70	2		T201	1		T336	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	327	1			T20	3		T121	1		T279	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	315	1			T20	3		T121	1		T63	5
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	30	1			T70	2		T287	1		T202	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	29	1			T74	3		T287	1		T201	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	18	1			T54	1		T63	1		T179	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T54	1		T36	1		T74	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	18	1			T199	1		T259	1		T38	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T202	1		T247	1		T151	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T63	1		T202	1		T259	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T259	2		T278	1		T266	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	288	1			T53	1		T59	1		T61	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	317	1			T53	1		T59	1		T61	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	41	1			T56	1		T234	1		T36	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T56	1		T234	1		T72	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T74	1		T179	1		T188	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T151	1		T159	3		T266	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	18	1			T50	1		T74	1		T291	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T70	1		T74	2		T259	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T56	1		T62	1		T74	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	12	1			T56	1		T199	1		T247	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	329	1			T18	1		T60	2		T61	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	328	1			T18	1		T60	2		T61	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T54	3		T291	1		T201	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	43	1			T54	3		T72	1		T36	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T74	2		T291	1		T201	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T74	1		T151	2		T266	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	29	1			T36	1		T194	1		T265	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T74	1		T259	1		T40	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T188	1		T151	1		T337	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T70	1		T265	1		T337	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	337	1			T5	1		T48	1		T121	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	327	1			T5	1		T121	1		T283	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	28	1			T57	1		T70	1		T235	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	32	1			T57	1		T201	1		T235	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T72	1		T50	1		T36	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	20	1			T63	1		T72	1		T74	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	29	1			T63	1		T50	1		T36	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	17	1			T259	1		T265	1		T338	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	22	1			T54	1		T72	1		T259	2
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	13	1			T54	1		T74	1		T278	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	325	1			T10	1		T18	3		T19	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	300	1			T10	1		T18	3		T19	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	51	1			T56	1		T70	1		T72	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T56	1		T63	1		T50	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	36	1			T63	1		T70	1		T74	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T74	2		T201	1		T200	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	19	1			T36	1		T151	1		T338	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	34	1			T70	1		T74	1		T277	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T36	2		T200	1		T231	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	12	1			T74	2		T199	1		T247	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	301	1			T59	1		T58	1		T62	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	310	1			T59	1		T58	1		T48	2