Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3851	1			T20	8		T53	6		T283	2
values[1]	3615	1			T60	12		T94	16		T48	20
values[2]	4000	1			T14	2		T75	16		T207	18
values[3]	3887	1			T18	10		T19	16		T121	4
values[4]	4307	1			T5	6		T56	6		T114	16
values[5]	4499	1			T64	10		T59	16		T55	24
values[6]	4231	1			T17	12		T61	18		T58	20
values[7]	3654	1			T10	4		T54	10		T62	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3682	1			T59	16		T60	12		T61	18
values[1]	4114	1			T48	20		T63	40		T110	14
values[2]	3681	1			T10	4		T64	10		T58	20
values[3]	4668	1			T14	2		T17	12		T53	6
values[4]	3284	1			T18	10		T20	8		T48	20
values[5]	4591	1			T5	6		T55	24		T62	20
values[6]	4125	1			T56	6		T207	18		T63	20
values[7]	3899	1			T19	16		T267	18		T255	8

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31245

1

T5

6

T10

4

T17

12

auto[1]

799

1

T14

2

T55

2

T63

11

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	407	1			T113	6		T38	19		T151	18
auto[0]	values[0]	values[1]	310	1			T67	24		T36	25		T201	20
auto[0]	values[0]	values[2]	356	1			T72	20		T316	4		T36	21
auto[0]	values[0]	values[3]	905	1			T53	6		T50	21		T74	130
auto[0]	values[0]	values[4]	407	1			T20	8		T69	19		T50	24
auto[0]	values[0]	values[5]	457	1			T283	2		T202	20		T259	20
auto[0]	values[0]	values[6]	512	1			T263	23		T247	18		T151	20
auto[0]	values[0]	values[7]	387	1			T273	10		T293	4		T50	34
auto[0]	values[1]	values[0]	373	1			T60	12		T63	18		T70	30
auto[0]	values[1]	values[1]	733	1			T315	2		T74	89		T223	20
auto[0]	values[1]	values[2]	380	1			T297	2		T307	2		T339	26
auto[0]	values[1]	values[3]	403	1			T94	16		T258	4		T291	26
auto[0]	values[1]	values[4]	371	1			T48	20		T201	20		T277	19
auto[0]	values[1]	values[5]	372	1			T284	4		T199	18		T112	4
auto[0]	values[1]	values[6]	630	1			T70	19		T269	31		T256	20
auto[0]	values[1]	values[7]	256	1			T306	2		T224	17		T266	23
auto[0]	values[2]	values[0]	518	1			T36	29		T74	60		T202	23
auto[0]	values[2]	values[1]	536	1			T110	14		T36	25		T201	134
auto[0]	values[2]	values[2]	536	1			T340	16		T179	20		T292	21
auto[0]	values[2]	values[3]	488	1			T75	16		T200	25		T259	17
auto[0]	values[2]	values[4]	304	1			T89	4		T159	22		T341	18
auto[0]	values[2]	values[5]	597	1			T301	2		T233	23		T336	6
auto[0]	values[2]	values[6]	520	1			T207	18		T68	22		T74	20
auto[0]	values[2]	values[7]	392	1			T255	8		T38	16		T342	8
auto[0]	values[3]	values[0]	554	1			T302	10		T343	10		T344	6
auto[0]	values[3]	values[1]	470	1			T261	14		T72	22		T233	20
auto[0]	values[3]	values[2]	483	1			T121	4		T70	20		T199	19
auto[0]	values[3]	values[3]	508	1			T200	19		T251	34		T40	39
auto[0]	values[3]	values[4]	456	1			T18	10		T246	4		T74	106
auto[0]	values[3]	values[5]	546	1			T230	56		T72	23		T259	94
auto[0]	values[3]	values[6]	320	1			T74	22		T251	24		T194	44
auto[0]	values[3]	values[7]	454	1			T19	16		T267	18		T36	27
auto[0]	values[4]	values[0]	464	1			T233	20		T38	26		T179	27
auto[0]	values[4]	values[1]	429	1			T48	20		T72	35		T292	39
auto[0]	values[4]	values[2]	398	1			T114	16		T287	8		T199	18
auto[0]	values[4]	values[3]	591	1			T57	16		T232	12		T256	19
auto[0]	values[4]	values[4]	595	1			T291	20		T305	6		T322	14
auto[0]	values[4]	values[5]	679	1			T5	6		T74	18		T201	32
auto[0]	values[4]	values[6]	508	1			T56	6		T254	52		T345	4
auto[0]	values[4]	values[7]	553	1			T298	14		T309	27		T303	18
auto[0]	values[5]	values[0]	537	1			T59	16		T279	16		T50	25
auto[0]	values[5]	values[1]	489	1			T202	19		T233	21		T194	19
auto[0]	values[5]	values[2]	665	1			T64	10		T95	20		T63	20
auto[0]	values[5]	values[3]	730	1			T71	14		T36	20		T74	33
auto[0]	values[5]	values[4]	317	1			T63	19		T73	6		T236	12
auto[0]	values[5]	values[5]	704	1			T55	22		T198	16		T65	69
auto[0]	values[5]	values[6]	294	1			T234	8		T346	4		T272	34
auto[0]	values[5]	values[7]	644	1			T74	125		T257	10		T201	20
auto[0]	values[6]	values[0]	356	1			T61	18		T111	4		T179	18
auto[0]	values[6]	values[1]	623	1			T63	20		T36	20		T201	40
auto[0]	values[6]	values[2]	438	1			T58	20		T122	2		T194	44
auto[0]	values[6]	values[3]	562	1			T17	12		T324	4		T238	18
auto[0]	values[6]	values[4]	300	1			T38	107		T251	28		T325	4
auto[0]	values[6]	values[5]	533	1			T63	18		T36	18		T274	16
auto[0]	values[6]	values[6]	773	1			T63	18		T300	20		T201	24
auto[0]	values[6]	values[7]	553	1			T36	57		T259	16		T347	2
auto[0]	values[7]	values[0]	366	1			T199	16		T201	51		T251	20
auto[0]	values[7]	values[1]	426	1			T63	19		T70	20		T285	6
auto[0]	values[7]	values[2]	339	1			T10	4		T313	10		T36	20
auto[0]	values[7]	values[3]	363	1			T54	10		T72	21		T308	10
auto[0]	values[7]	values[4]	456	1			T249	6		T74	55		T233	20
auto[0]	values[7]	values[5]	585	1			T62	20		T63	37		T66	84
auto[0]	values[7]	values[6]	476	1			T250	20		T200	22		T265	59
auto[0]	values[7]	values[7]	558	1			T251	21		T264	26		T195	16
auto[1]	values[0]	values[0]	13	1			T38	1		T151	2		T252	1
auto[1]	values[0]	values[1]	7	1			T262	1		T348	4		T349	1
auto[1]	values[0]	values[2]	10	1			T36	1		T292	2		T295	1
auto[1]	values[0]	values[3]	31	1			T74	6		T40	4		T330	2
auto[1]	values[0]	values[4]	8	1			T69	1		T256	1		T278	1
auto[1]	values[0]	values[5]	13	1			T202	1		T38	1		T224	2
auto[1]	values[0]	values[6]	12	1			T247	2		T260	1		T295	2
auto[1]	values[0]	values[7]	16	1			T38	2		T188	2		T194	2
auto[1]	values[1]	values[0]	11	1			T63	2		T70	2		T350	1
auto[1]	values[1]	values[1]	17	1			T74	1		T180	1		T327	1
auto[1]	values[1]	values[2]	9	1			T351	1		T241	1		T352	3
auto[1]	values[1]	values[3]	5	1			T291	1		T330	2		T353	1
auto[1]	values[1]	values[4]	10	1			T277	1		T202	3		T247	4
auto[1]	values[1]	values[5]	15	1			T199	2		T201	1		T260	2
auto[1]	values[1]	values[6]	21	1			T70	1		T278	1		T266	2
auto[1]	values[1]	values[7]	9	1			T224	3		T319	1		T354	1
auto[1]	values[2]	values[0]	14	1			T233	2		T188	1		T263	1
auto[1]	values[2]	values[1]	10	1			T201	3		T38	1		T256	2
auto[1]	values[2]	values[2]	15	1			T292	3		T332	1		T355	2
auto[1]	values[2]	values[3]	17	1			T14	2		T200	1		T259	3
auto[1]	values[2]	values[4]	10	1			T295	3		T42	2		T356	2
auto[1]	values[2]	values[5]	14	1			T278	1		T266	1		T332	1
auto[1]	values[2]	values[6]	10	1			T38	1		T188	2		T263	2
auto[1]	values[2]	values[7]	19	1			T38	4		T247	2		T330	5
auto[1]	values[3]	values[0]	19	1			T266	5		T272	1		T357	6
auto[1]	values[3]	values[1]	15	1			T244	1		T42	5		T351	1
auto[1]	values[3]	values[2]	6	1			T199	1		T42	1		T358	2
auto[1]	values[3]	values[3]	13	1			T200	3		T40	2		T359	1
auto[1]	values[3]	values[4]	12	1			T74	3		T201	2		T278	1
auto[1]	values[3]	values[5]	16	1			T259	1		T360	2		T266	3
auto[1]	values[3]	values[6]	9	1			T251	1		T159	2		T260	2
auto[1]	values[3]	values[7]	6	1			T244	2		T80	1		T241	1
auto[1]	values[4]	values[0]	10	1			T38	1		T188	1		T278	1
auto[1]	values[4]	values[1]	8	1			T72	1		T361	2		T362	1
auto[1]	values[4]	values[2]	12	1			T199	2		T224	1		T363	1
auto[1]	values[4]	values[3]	5	1			T256	1		T244	1		T350	1
auto[1]	values[4]	values[4]	19	1			T151	1		T327	4		T182	1
auto[1]	values[4]	values[5]	15	1			T74	2		T201	2		T194	2
auto[1]	values[4]	values[6]	10	1			T265	2		T231	1		T364	3
auto[1]	values[4]	values[7]	11	1			T231	4		T332	1		T260	2
auto[1]	values[5]	values[0]	16	1			T202	2		T266	4		T240	5
auto[1]	values[5]	values[1]	15	1			T202	1		T194	1		T225	1
auto[1]	values[5]	values[2]	9	1			T251	2		T332	1		T226	1
auto[1]	values[5]	values[3]	22	1			T71	2		T326	2		T272	2
auto[1]	values[5]	values[4]	11	1			T63	1		T73	2		T231	2
auto[1]	values[5]	values[5]	19	1			T55	2		T79	1		T365	5
auto[1]	values[5]	values[6]	8	1			T272	6		T358	2		-	-
auto[1]	values[5]	values[7]	19	1			T74	2		T265	1		T247	2
auto[1]	values[6]	values[0]	10	1			T179	3		T278	1		T180	2
auto[1]	values[6]	values[1]	14	1			T201	1		T330	1		T366	1
auto[1]	values[6]	values[2]	18	1			T194	3		T240	1		T79	2
auto[1]	values[6]	values[3]	9	1			T265	2		T295	2		T242	1
auto[1]	values[6]	values[4]	3	1			T38	1		T251	2		-	-
auto[1]	values[6]	values[5]	12	1			T63	2		T36	2		T292	2
auto[1]	values[6]	values[6]	12	1			T63	2		T201	2		T38	1
auto[1]	values[6]	values[7]	15	1			T36	2		T259	4		T151	1
auto[1]	values[7]	values[0]	14	1			T199	4		T201	2		T188	1
auto[1]	values[7]	values[1]	12	1			T63	1		T330	1		T367	2
auto[1]	values[7]	values[2]	7	1			T265	4		T367	1		T365	1
auto[1]	values[7]	values[3]	16	1			T179	2		T231	1		T240	1
auto[1]	values[7]	values[4]	5	1			T74	2		T265	1		T248	1
auto[1]	values[7]	values[5]	14	1			T63	3		T368	1		T228	1
auto[1]	values[7]	values[6]	10	1			T265	4		T241	1		T356	2
auto[1]	values[7]	values[7]	7	1			T367	2		T369	1		T161	1