Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	702	1			T34	10		T35	7		T37	18
all_values[1]	702	1			T34	10		T35	7		T37	18
all_values[2]	702	1			T34	10		T35	7		T37	18
all_values[3]	702	1			T34	10		T35	7		T37	18
all_values[4]	702	1			T34	10		T35	7		T37	18
all_values[5]	702	1			T34	10		T35	7		T37	18
all_values[6]	702	1			T34	10		T35	7		T37	18
all_values[7]	702	1			T34	10		T35	7		T37	18

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2969

1

T34

50

T35

27

T37

72

auto[1]

2647

1

T34

30

T35

29

T37

72

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2215

1

T34

31

T35

18

T37

64

auto[1]

3401

1

T34

49

T35

38

T37

80

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3176

1

T34

48

T35

27

T37

88

auto[1]

2440

1

T34

32

T35

29

T37

56

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	143	1			T35	1		T37	3		T38	6
all_values[0]	auto[0]	auto[0]	auto[1]	72	1			T34	4		T37	2		T38	2
all_values[0]	auto[0]	auto[1]	auto[0]	120	1			T34	1		T35	1		T37	2
all_values[0]	auto[0]	auto[1]	auto[1]	55	1			T37	3		T38	1		T196	2
all_values[0]	auto[1]	auto[0]	auto[1]	171	1			T34	3		T35	3		T37	4
all_values[0]	auto[1]	auto[1]	auto[1]	141	1			T34	2		T35	2		T37	4
all_values[1]	auto[0]	auto[0]	auto[0]	127	1			T34	2		T35	1		T37	2
all_values[1]	auto[0]	auto[0]	auto[1]	62	1			T34	4		T37	1		T38	2
all_values[1]	auto[0]	auto[1]	auto[0]	115	1			T34	3		T35	1		T37	5
all_values[1]	auto[0]	auto[1]	auto[1]	80	1			T35	1		T37	2		T38	2
all_values[1]	auto[1]	auto[0]	auto[1]	174	1			T35	2		T37	7		T38	5
all_values[1]	auto[1]	auto[1]	auto[1]	144	1			T34	1		T35	2		T37	1
all_values[2]	auto[0]	auto[0]	auto[0]	140	1			T34	6		T35	1		T37	3
all_values[2]	auto[0]	auto[0]	auto[1]	72	1			T34	1		T35	1		T37	1
all_values[2]	auto[0]	auto[1]	auto[0]	119	1			T34	1		T35	2		T37	8
all_values[2]	auto[0]	auto[1]	auto[1]	75	1			T35	1		T37	1		T38	2
all_values[2]	auto[1]	auto[0]	auto[1]	153	1			T34	2		T35	1		T37	3
all_values[2]	auto[1]	auto[1]	auto[1]	143	1			T35	1		T37	2		T38	6
all_values[3]	auto[0]	auto[0]	auto[0]	139	1			T34	2		T37	2		T38	6
all_values[3]	auto[0]	auto[0]	auto[1]	63	1			T34	1		T35	1		T38	2
all_values[3]	auto[0]	auto[1]	auto[0]	124	1			T35	1		T37	7		T196	6
all_values[3]	auto[0]	auto[1]	auto[1]	62	1			T34	1		T37	1		T38	2
all_values[3]	auto[1]	auto[0]	auto[1]	168	1			T34	2		T35	4		T37	2
all_values[3]	auto[1]	auto[1]	auto[1]	146	1			T34	4		T35	1		T37	6
all_values[4]	auto[0]	auto[0]	auto[0]	134	1			T34	3		T37	3		T196	1
all_values[4]	auto[0]	auto[0]	auto[1]	75	1			T34	2		T35	1		T37	2
all_values[4]	auto[0]	auto[1]	auto[0]	119	1			T34	1		T35	2		T37	3
all_values[4]	auto[0]	auto[1]	auto[1]	65	1			T37	3		T38	1		T196	5
all_values[4]	auto[1]	auto[0]	auto[1]	162	1			T34	3		T37	5		T38	4
all_values[4]	auto[1]	auto[1]	auto[1]	147	1			T34	1		T35	4		T37	2
all_values[5]	auto[0]	auto[0]	auto[0]	216	1			T34	5		T35	1		T37	10
all_values[5]	auto[0]	auto[1]	auto[0]	191	1			T34	2		T35	2		T37	2
all_values[5]	auto[1]	auto[0]	auto[1]	149	1			T34	1		T35	4		T37	4
all_values[5]	auto[1]	auto[1]	auto[1]	146	1			T34	2		T37	2		T38	4
all_values[6]	auto[0]	auto[0]	auto[0]	137	1			T34	1		T37	2		T38	9
all_values[6]	auto[0]	auto[0]	auto[1]	59	1			T34	2		T35	2		T196	1
all_values[6]	auto[0]	auto[1]	auto[0]	118	1			T34	1		T37	5		T38	4
all_values[6]	auto[0]	auto[1]	auto[1]	82	1			T35	2		T37	3		T197	1
all_values[6]	auto[1]	auto[0]	auto[1]	184	1			T34	5		T35	1		T37	5
all_values[6]	auto[1]	auto[1]	auto[1]	122	1			T34	1		T35	2		T37	3
all_values[7]	auto[0]	auto[0]	auto[0]	151	1			T34	1		T35	2		T37	5
all_values[7]	auto[0]	auto[0]	auto[1]	65	1			T37	4		T38	1		T196	2
all_values[7]	auto[0]	auto[1]	auto[0]	122	1			T34	2		T35	3		T37	2
all_values[7]	auto[0]	auto[1]	auto[1]	74	1			T34	2		T37	1		T38	1
all_values[7]	auto[1]	auto[0]	auto[1]	153	1			T35	1		T37	2		T38	3
all_values[7]	auto[1]	auto[1]	auto[1]	137	1			T34	5		T35	1		T37	4

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal