Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2088

1

T4

2

T11

1

T13

3

auto[1]

2063

1

T4

2

T13

3

T25

22

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2213

1

T13

3

T43

9

T47

12

auto[1]

1938

1

T4

4

T11

1

T13

3

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3324

1

T4

4

T11

1

T13

6

auto[1]

827

1

T43

4

T47

7

T48

3

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	843	1			T4	1		T25	10		T26	8
valid[1]	886	1			T13	2		T25	9		T26	7
valid[2]	821	1			T4	1		T13	1		T25	4
valid[3]	825	1			T4	1		T11	1		T13	2
valid[4]	776	1			T4	1		T13	1		T25	4

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	137	1			T49	1		T123	3		T72	1
auto[0]	auto[0]	valid[0]	auto[1]	197	1			T4	1		T25	3		T26	5
auto[0]	auto[0]	valid[1]	auto[0]	142	1			T48	2		T96	1		T62	1
auto[0]	auto[0]	valid[1]	auto[1]	206	1			T25	3		T26	3		T28	1
auto[0]	auto[0]	valid[2]	auto[0]	137	1			T43	1		T49	1		T34	1
auto[0]	auto[0]	valid[2]	auto[1]	199	1			T13	1		T25	1		T26	3
auto[0]	auto[0]	valid[3]	auto[0]	149	1			T13	1		T123	1		T383	1
auto[0]	auto[0]	valid[3]	auto[1]	189	1			T11	1		T25	1		T26	1
auto[0]	auto[0]	valid[4]	auto[0]	124	1			T43	1		T47	2		T48	1
auto[0]	auto[0]	valid[4]	auto[1]	194	1			T4	1		T13	1		T25	2
auto[0]	auto[1]	valid[0]	auto[0]	144	1			T43	1		T47	1		T49	3
auto[0]	auto[1]	valid[0]	auto[1]	190	1			T25	7		T26	3		T30	3
auto[0]	auto[1]	valid[1]	auto[0]	144	1			T13	2		T43	1		T48	1
auto[0]	auto[1]	valid[1]	auto[1]	211	1			T25	6		T26	4		T30	1
auto[0]	auto[1]	valid[2]	auto[0]	146	1			T49	1		T96	2		T69	1
auto[0]	auto[1]	valid[2]	auto[1]	185	1			T4	1		T25	3		T26	4
auto[0]	auto[1]	valid[3]	auto[0]	133	1			T96	3		T62	1		T383	1
auto[0]	auto[1]	valid[3]	auto[1]	189	1			T4	1		T13	1		T25	4
auto[0]	auto[1]	valid[4]	auto[0]	130	1			T43	1		T47	2		T48	1
auto[0]	auto[1]	valid[4]	auto[1]	178	1			T25	2		T26	3		T30	1
auto[1]	auto[0]	valid[0]	auto[0]	95	1			T43	1		T47	1		T48	1
auto[1]	auto[0]	valid[1]	auto[0]	95	1			T47	2		T49	3		T96	2
auto[1]	auto[0]	valid[2]	auto[0]	69	1			T43	1		T49	2		T96	1
auto[1]	auto[0]	valid[3]	auto[0]	86	1			T49	2		T96	2		T62	1
auto[1]	auto[0]	valid[4]	auto[0]	69	1			T47	1		T62	1		T69	1
auto[1]	auto[1]	valid[0]	auto[0]	80	1			T43	1		T47	1		T48	1
auto[1]	auto[1]	valid[1]	auto[0]	88	1			T96	3		T69	1		T123	3
auto[1]	auto[1]	valid[2]	auto[0]	85	1			T49	2		T96	2		T69	1
auto[1]	auto[1]	valid[3]	auto[0]	79	1			T43	1		T48	1		T62	1
auto[1]	auto[1]	valid[4]	auto[0]	81	1			T47	2		T69	1		T123	2

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal