Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

55225

1

T3

1

T12

2

T13

125

auto[1]

20727

1

T4

4

T11

1

T13

44

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

55553

1

T3

1

T4

4

T11

1

auto[1]

20399

1

T12

1

T13

41

T29

4

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	39007	1			T4	4		T11	1		T12	1
others[1]	6458	1			T13	11		T25	38		T26	27
others[2]	6460	1			T3	1		T13	9		T25	20
others[3]	7273	1			T12	1		T13	16		T25	34
interest[1]	4259	1			T13	12		T25	14		T26	25
interest[4]	25258	1			T4	4		T11	1		T12	1
interest[64]	12495	1			T13	36		T25	47		T26	65

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	17691	1			T12	1		T13	40		T29	4
auto[0]	auto[0]	others[1]	2959	1			T13	5		T32	1		T43	8
auto[0]	auto[0]	others[2]	3001	1			T3	1		T13	4		T43	8
auto[0]	auto[0]	others[3]	3341	1			T13	5		T29	1		T43	14
auto[0]	auto[0]	interest[1]	2011	1			T13	7		T43	10		T47	16
auto[0]	auto[0]	interest[4]	11367	1			T12	1		T13	22		T29	3
auto[0]	auto[0]	interest[64]	5823	1			T13	23		T29	2		T32	2
auto[0]	auto[1]	others[0]	10934	1			T4	4		T11	1		T13	24
auto[0]	auto[1]	others[1]	1781	1			T13	3		T25	38		T26	27
auto[0]	auto[1]	others[2]	1688	1			T13	3		T25	20		T26	26
auto[0]	auto[1]	others[3]	1964	1			T13	3		T25	34		T26	40
auto[0]	auto[1]	interest[1]	1095	1			T13	4		T25	14		T26	25
auto[0]	auto[1]	interest[4]	7193	1			T4	4		T11	1		T13	20
auto[0]	auto[1]	interest[64]	3265	1			T13	7		T25	47		T26	65
auto[1]	auto[0]	others[0]	10382	1			T13	21		T29	2		T32	1
auto[1]	auto[0]	others[1]	1718	1			T13	3		T43	10		T47	14
auto[1]	auto[0]	others[2]	1771	1			T13	2		T29	1		T43	14
auto[1]	auto[0]	others[3]	1968	1			T12	1		T13	8		T32	1
auto[1]	auto[0]	interest[1]	1153	1			T13	1		T29	1		T43	6
auto[1]	auto[0]	interest[4]	6698	1			T13	12		T29	2		T43	35
auto[1]	auto[0]	interest[64]	3407	1			T13	6		T43	20		T47	16

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal