Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3507664	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4286895

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4212921	1			T1	67		T2	1		T3	1
values[0x0]	1789058	1			T4	20		T5	214		T6	428
values[0x1]	1792580	1			T3	1		T4	20		T5	220

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2487968	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5306591

1

T1

25

T2

1

T3

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29666	1			T1	3		T4	5		T5	10
valid_sources[0x01]	30554	1			T5	4		T6	3		T7	6
valid_sources[0x02]	29497	1			T4	1		T5	6		T6	1
valid_sources[0x03]	31725	1			T1	8		T4	2		T5	2
valid_sources[0x04]	31068	1			T4	2		T5	3		T6	2
valid_sources[0x05]	28749	1			T6	3		T7	5		T8	5
valid_sources[0x06]	28314	1			T4	2		T5	1		T6	2
valid_sources[0x07]	27324	1			T5	5		T6	2		T7	8
valid_sources[0x08]	30820	1			T4	7		T5	5		T6	3
valid_sources[0x09]	28135	1			T4	3		T5	4		T6	6
valid_sources[0x0a]	27144	1			T5	2		T6	4		T7	5
valid_sources[0x0b]	30561	1			T1	6		T5	6		T6	10
valid_sources[0x0c]	28003	1			T5	1		T6	2		T7	2
valid_sources[0x0d]	29342	1			T6	2		T7	4		T8	6
valid_sources[0x0e]	31881	1			T4	4		T5	12		T6	6
valid_sources[0x0f]	31169	1			T1	3		T5	4		T6	5
valid_sources[0x10]	33369	1			T1	4		T5	4		T6	11
valid_sources[0x11]	29547	1			T5	1		T6	2		T7	6
valid_sources[0x12]	28979	1			T5	1		T7	3		T8	1
valid_sources[0x13]	28425	1			T5	2		T6	4		T7	3
valid_sources[0x14]	29047	1			T5	6		T6	1		T7	4
valid_sources[0x15]	28528	1			T5	6		T8	6		T11	3
valid_sources[0x16]	29682	1			T5	8		T6	3		T7	3
valid_sources[0x17]	33216	1			T4	11		T5	8		T6	6
valid_sources[0x18]	30352	1			T5	4		T6	3		T7	7
valid_sources[0x19]	30549	1			T4	1		T5	1		T6	2
valid_sources[0x1a]	31809	1			T4	2		T5	4		T7	2
valid_sources[0x1b]	35585	1			T6	2		T7	4		T8	8
valid_sources[0x1c]	36213	1			T4	4		T5	7		T6	6
valid_sources[0x1d]	28227	1			T5	1		T6	4		T7	3
valid_sources[0x1e]	29869	1			T5	3		T6	1		T7	8
valid_sources[0x1f]	29353	1			T1	2		T4	5		T5	3
valid_sources[0x20]	27093	1			T5	3		T6	10		T7	6
valid_sources[0x21]	38784	1			T4	2		T5	3		T6	3
valid_sources[0x22]	30702	1			T4	9		T5	2		T6	5
valid_sources[0x23]	27258	1			T5	5		T6	2		T7	3
valid_sources[0x24]	30949	1			T5	4		T6	14		T7	4
valid_sources[0x25]	30485	1			T4	5		T5	2		T6	5
valid_sources[0x26]	30397	1			T4	4		T5	2		T7	11
valid_sources[0x27]	29791	1			T4	1		T5	2		T6	5
valid_sources[0x28]	28176	1			T4	3		T5	3		T6	4
valid_sources[0x29]	29385	1			T5	2		T6	4		T7	2
valid_sources[0x2a]	31711	1			T4	10		T5	5		T6	8
valid_sources[0x2b]	30457	1			T4	1		T5	1		T6	1
valid_sources[0x2c]	32466	1			T4	1		T5	6		T6	2
valid_sources[0x2d]	29980	1			T4	2		T5	6		T6	2
valid_sources[0x2e]	30355	1			T5	6		T6	9		T7	5
valid_sources[0x2f]	27895	1			T4	1		T5	2		T7	5
valid_sources[0x30]	28864	1			T5	3		T6	1		T7	2
valid_sources[0x31]	32190	1			T4	1		T5	5		T7	1
valid_sources[0x32]	28336	1			T4	1		T5	7		T6	2
valid_sources[0x33]	30339	1			T4	1		T5	6		T7	3
valid_sources[0x34]	27382	1			T6	6		T7	4		T8	1
valid_sources[0x35]	31533	1			T4	2		T5	4		T6	2
valid_sources[0x36]	28295	1			T1	1		T4	4		T5	3
valid_sources[0x37]	28728	1			T5	5		T7	8		T8	1
valid_sources[0x38]	29134	1			T4	12		T5	10		T6	6
valid_sources[0x39]	28846	1			T4	8		T5	2		T7	5
valid_sources[0x3a]	29756	1			T5	5		T7	3		T8	3
valid_sources[0x3b]	54211	1			T5	2		T6	1		T7	3
valid_sources[0x3c]	29754	1			T4	1		T5	1		T6	5
valid_sources[0x3d]	29844	1			T7	2		T8	1		T12	9
valid_sources[0x3e]	29310	1			T4	11		T5	3		T7	4
valid_sources[0x3f]	29572	1			T4	10		T5	2		T6	1
valid_sources[0x40]	29070	1			T5	6		T6	3		T7	1
valid_sources[0x41]	32951	1			T5	4		T6	3		T7	2
valid_sources[0x42]	31043	1			T5	2		T6	6		T7	6
valid_sources[0x43]	29742	1			T1	4		T5	3		T6	2
valid_sources[0x44]	30272	1			T5	9		T6	6		T7	1
valid_sources[0x45]	29807	1			T4	2		T5	1		T6	3
valid_sources[0x46]	31739	1			T4	6		T5	4		T6	5
valid_sources[0x47]	30683	1			T4	9		T5	3		T6	1
valid_sources[0x48]	28357	1			T1	2		T5	6		T6	3
valid_sources[0x49]	28943	1			T5	7		T6	5		T7	6
valid_sources[0x4a]	29557	1			T4	7		T5	3		T6	5
valid_sources[0x4b]	33593	1			T4	1		T5	2		T6	2
valid_sources[0x4c]	33484	1			T4	2		T5	1		T7	5
valid_sources[0x4d]	29288	1			T4	2		T5	2		T7	1
valid_sources[0x4e]	27641	1			T4	3		T5	5		T6	3
valid_sources[0x4f]	28028	1			T4	8		T6	9		T7	6
valid_sources[0x50]	29876	1			T4	1		T5	3		T6	2
valid_sources[0x51]	28154	1			T5	2		T7	4		T8	2
valid_sources[0x52]	29784	1			T4	3		T5	6		T7	8
valid_sources[0x53]	34172	1			T4	1		T5	2		T6	3
valid_sources[0x54]	28646	1			T4	2		T5	4		T6	1
valid_sources[0x55]	37221	1			T1	2		T4	6		T5	4
valid_sources[0x56]	27987	1			T5	2		T6	3		T7	4
valid_sources[0x57]	33648	1			T4	3		T5	1		T6	2
valid_sources[0x58]	30474	1			T4	7		T5	4		T6	1
valid_sources[0x59]	31735	1			T4	6		T5	2		T6	3
valid_sources[0x5a]	30646	1			T5	7		T6	4		T7	3
valid_sources[0x5b]	29814	1			T4	2		T5	3		T6	1
valid_sources[0x5c]	28316	1			T5	2		T6	6		T7	9
valid_sources[0x5d]	47262	1			T5	5		T7	4		T8	7
valid_sources[0x5e]	29936	1			T5	2		T6	2		T7	5
valid_sources[0x5f]	31378	1			T4	1		T5	4		T7	1
valid_sources[0x60]	31366	1			T5	2		T6	4		T7	3
valid_sources[0x61]	32891	1			T4	1		T5	2		T6	2
valid_sources[0x62]	29010	1			T5	5		T6	4		T7	3
valid_sources[0x63]	31453	1			T4	1		T5	5		T6	6
valid_sources[0x64]	32462	1			T4	6		T5	4		T6	7
valid_sources[0x65]	27497	1			T4	1		T5	7		T7	1
valid_sources[0x66]	36559	1			T4	2		T5	4		T6	3
valid_sources[0x67]	30466	1			T4	5		T5	4		T7	7
valid_sources[0x68]	29370	1			T5	7		T6	4		T7	3
valid_sources[0x69]	32267	1			T4	7		T5	6		T6	4
valid_sources[0x6a]	28628	1			T5	6		T6	7		T7	4
valid_sources[0x6b]	29992	1			T4	1		T5	3		T6	1
valid_sources[0x6c]	27377	1			T5	1		T6	2		T7	3
valid_sources[0x6d]	30123	1			T5	2		T6	2		T7	6
valid_sources[0x6e]	29704	1			T4	10		T6	6		T7	3
valid_sources[0x6f]	31418	1			T5	6		T6	1		T7	3
valid_sources[0x70]	28655	1			T4	1		T5	6		T6	1
valid_sources[0x71]	28926	1			T1	2		T5	2		T6	5
valid_sources[0x72]	29226	1			T5	4		T6	2		T7	2
valid_sources[0x73]	28460	1			T1	1		T4	1		T5	5
valid_sources[0x74]	27228	1			T4	4		T5	6		T6	4
valid_sources[0x75]	35442	1			T4	3		T5	1		T6	4
valid_sources[0x76]	33389	1			T4	3		T5	4		T6	1
valid_sources[0x77]	30537	1			T5	1		T6	3		T7	4
valid_sources[0x78]	28906	1			T4	1		T5	3		T6	1
valid_sources[0x79]	30487	1			T1	1		T5	9		T6	3
valid_sources[0x7a]	33053	1			T5	3		T6	5		T7	5
valid_sources[0x7b]	29677	1			T4	7		T5	3		T7	6
valid_sources[0x7c]	30254	1			T5	4		T6	5		T7	4
valid_sources[0x7d]	34866	1			T4	1		T5	3		T7	1
valid_sources[0x7e]	29799	1			T7	5		T11	1		T12	5
valid_sources[0x7f]	29176	1			T4	10		T5	2		T6	3
valid_sources[0x80]	28871	1			T5	2		T6	22		T7	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1021915

1

T1

1

T2

1

T3

1

values[0x0]

all_enables

biggest_size

1643138

1

T4

10

T5

149

T6

427

values[0x1]

all_enables

biggest_size

1621842

1

T4

9

T5

151

T6

465