Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3536191

1

T1

66

T3

1

T4

516

full_word

4288553

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7824264	1			T1	67		T2	1		T3	2
auto[TlIntgErrCmd]	172	1			T133	7		T134	1		T135	16
auto[TlIntgErrData]	148	1			T133	7		T134	4		T135	9
auto[TlIntgErrBoth]	160	1			T133	6		T134	5		T135	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4218737

1

T1

67

T2

1

T3

1

auto[1]

3606007

1

T3

1

T4

40

T5

434

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3196165	1			T1	66		T4	495		T5	387
auto[TlIntgErrNone]	partial	auto[1]	339581	1			T3	1		T4	21		T5	134
auto[TlIntgErrNone]	full_word	auto[0]	1022357	1			T1	1		T2	1		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	3266161	1			T4	19		T5	300		T6	892
auto[TlIntgErrCmd]	partial	auto[0]	73	1			T133	3		T135	5		T212	8
auto[TlIntgErrCmd]	partial	auto[1]	90	1			T133	3		T134	1		T135	11
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T215	1		T216	1		T217	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T133	1		T142	1		T216	1
auto[TlIntgErrData]	partial	auto[0]	68	1			T133	3		T134	3		T135	5
auto[TlIntgErrData]	partial	auto[1]	69	1			T133	3		T134	1		T135	4
auto[TlIntgErrData]	full_word	auto[0]	3	1			T218	1		T219	1		T220	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T133	1		T185	1		T213	1
auto[TlIntgErrBoth]	partial	auto[0]	62	1			T133	3		T134	1		T135	2
auto[TlIntgErrBoth]	partial	auto[1]	83	1			T133	2		T134	4		T135	1
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T142	1		T221	2		T218	2
auto[TlIntgErrBoth]	full_word	auto[1]	9	1			T133	1		T135	2		T212	1