Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	503894702	3064821	0	0
DepthKnown_A	503894702	503753621	0	0
RvalidKnown_A	503894702	503753621	0	0
WreadyKnown_A	503894702	503753621	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	3064821	0	0
T6	25116	832	0	0
T7	7195	832	0	0
T8	31585	1666	0	0
T9	128131	832	0	0
T10	131477	832	0	0
T11	568143	0	0	0
T12	104265	832	0	0
T13	121765	832	0	0
T14	45098	832	0	0
T15	5288	0	0	0
T17	0	832	0	0
T18	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	503753621	0	0
T1	1469	1398	0	0
T2	1563	1467	0	0
T3	929	857	0	0
T4	10082	10010	0	0
T5	26948	26878	0	0
T6	25116	25038	0	0
T7	7195	7111	0	0
T8	31585	31519	0	0
T9	128131	128043	0	0
T10	131477	131413	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	503753621	0	0
T1	1469	1398	0	0
T2	1563	1467	0	0
T3	929	857	0	0
T4	10082	10010	0	0
T5	26948	26878	0	0
T6	25116	25038	0	0
T7	7195	7111	0	0
T8	31585	31519	0	0
T9	128131	128043	0	0
T10	131477	131413	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	503753621	0	0
T1	1469	1398	0	0
T2	1563	1467	0	0
T3	929	857	0	0
T4	10082	10010	0	0
T5	26948	26878	0	0
T6	25116	25038	0	0
T7	7195	7111	0	0
T8	31585	31519	0	0
T9	128131	128043	0	0
T10	131477	131413	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	503894702	3287512	0	0
DepthKnown_A	503894702	503753621	0	0
RvalidKnown_A	503894702	503753621	0	0
WreadyKnown_A	503894702	503753621	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	3287512	0	0
T6	25116	832	0	0
T7	7195	832	0	0
T8	31585	835	0	0
T9	128131	2663	0	0
T10	131477	832	0	0
T11	568143	0	0	0
T12	104265	2496	0	0
T13	121765	2561	0	0
T14	45098	832	0	0
T15	5288	0	0	0
T17	0	832	0	0
T18	0	3876	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	503753621	0	0
T1	1469	1398	0	0
T2	1563	1467	0	0
T3	929	857	0	0
T4	10082	10010	0	0
T5	26948	26878	0	0
T6	25116	25038	0	0
T7	7195	7111	0	0
T8	31585	31519	0	0
T9	128131	128043	0	0
T10	131477	131413	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	503753621	0	0
T1	1469	1398	0	0
T2	1563	1467	0	0
T3	929	857	0	0
T4	10082	10010	0	0
T5	26948	26878	0	0
T6	25116	25038	0	0
T7	7195	7111	0	0
T8	31585	31519	0	0
T9	128131	128043	0	0
T10	131477	131413	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	503753621	0	0
T1	1469	1398	0	0
T2	1563	1467	0	0
T3	929	857	0	0
T4	10082	10010	0	0
T5	26948	26878	0	0
T6	25116	25038	0	0
T7	7195	7111	0	0
T8	31585	31519	0	0
T9	128131	128043	0	0
T10	131477	131413	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T4 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	503894702	186235	0	0
DepthKnown_A	503894702	503753621	0	0
RvalidKnown_A	503894702	503753621	0	0
WreadyKnown_A	503894702	503753621	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	186235	0	0
T4	10082	19	0	0
T5	26948	151	0	0
T6	25116	0	0	0
T7	7195	0	0	0
T8	31585	0	0	0
T9	128131	0	0	0
T10	131477	0	0	0
T11	568143	0	0	0
T12	104265	0	0	0
T13	121765	0	0	0
T27	0	22	0	0
T28	0	488	0	0
T31	0	25	0	0
T33	0	1	0	0
T43	0	288	0	0
T44	0	11	0	0
T45	0	276	0	0
T46	0	29	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	503753621	0	0
T1	1469	1398	0	0
T2	1563	1467	0	0
T3	929	857	0	0
T4	10082	10010	0	0
T5	26948	26878	0	0
T6	25116	25038	0	0
T7	7195	7111	0	0
T8	31585	31519	0	0
T9	128131	128043	0	0
T10	131477	131413	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	503753621	0	0
T1	1469	1398	0	0
T2	1563	1467	0	0
T3	929	857	0	0
T4	10082	10010	0	0
T5	26948	26878	0	0
T6	25116	25038	0	0
T7	7195	7111	0	0
T8	31585	31519	0	0
T9	128131	128043	0	0
T10	131477	131413	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	503753621	0	0
T1	1469	1398	0	0
T2	1563	1467	0	0
T3	929	857	0	0
T4	10082	10010	0	0
T5	26948	26878	0	0
T6	25116	25038	0	0
T7	7195	7111	0	0
T8	31585	31519	0	0
T9	128131	128043	0	0
T10	131477	131413	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	503894702	370586	0	0
DepthKnown_A	503894702	503753621	0	0
RvalidKnown_A	503894702	503753621	0	0
WreadyKnown_A	503894702	503753621	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	370586	0	0
T4	10082	48	0	0
T5	26948	151	0	0
T6	25116	0	0	0
T7	7195	0	0	0
T8	31585	0	0	0
T9	128131	0	0	0
T10	131477	0	0	0
T11	568143	0	0	0
T12	104265	0	0	0
T13	121765	0	0	0
T27	0	22	0	0
T28	0	2265	0	0
T31	0	87	0	0
T33	0	1	0	0
T43	0	288	0	0
T44	0	11	0	0
T45	0	1268	0	0
T46	0	29	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	503753621	0	0
T1	1469	1398	0	0
T2	1563	1467	0	0
T3	929	857	0	0
T4	10082	10010	0	0
T5	26948	26878	0	0
T6	25116	25038	0	0
T7	7195	7111	0	0
T8	31585	31519	0	0
T9	128131	128043	0	0
T10	131477	131413	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	503753621	0	0
T1	1469	1398	0	0
T2	1563	1467	0	0
T3	929	857	0	0
T4	10082	10010	0	0
T5	26948	26878	0	0
T6	25116	25038	0	0
T7	7195	7111	0	0
T8	31585	31519	0	0
T9	128131	128043	0	0
T10	131477	131413	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	503753621	0	0
T1	1469	1398	0	0
T2	1563	1467	0	0
T3	929	857	0	0
T4	10082	10010	0	0
T5	26948	26878	0	0
T6	25116	25038	0	0
T7	7195	7111	0	0
T8	31585	31519	0	0
T9	128131	128043	0	0
T10	131477	131413	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	503894702	6009013	0	0
DepthKnown_A	503894702	503753621	0	0
RvalidKnown_A	503894702	503753621	0	0
WreadyKnown_A	503894702	503753621	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	6009013	0	0
T1	1469	67	0	0
T2	1563	1	0	0
T3	929	2	0	0
T4	10082	540	0	0
T5	26948	848	0	0
T6	25116	72	0	0
T7	7195	219	0	0
T8	31585	98	0	0
T9	128131	5020	0	0
T10	131477	63	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	503753621	0	0
T1	1469	1398	0	0
T2	1563	1467	0	0
T3	929	857	0	0
T4	10082	10010	0	0
T5	26948	26878	0	0
T6	25116	25038	0	0
T7	7195	7111	0	0
T8	31585	31519	0	0
T9	128131	128043	0	0
T10	131477	131413	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	503753621	0	0
T1	1469	1398	0	0
T2	1563	1467	0	0
T3	929	857	0	0
T4	10082	10010	0	0
T5	26948	26878	0	0
T6	25116	25038	0	0
T7	7195	7111	0	0
T8	31585	31519	0	0
T9	128131	128043	0	0
T10	131477	131413	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	503753621	0	0
T1	1469	1398	0	0
T2	1563	1467	0	0
T3	929	857	0	0
T4	10082	10010	0	0
T5	26948	26878	0	0
T6	25116	25038	0	0
T7	7195	7111	0	0
T8	31585	31519	0	0
T9	128131	128043	0	0
T10	131477	131413	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	503894702	11380831	0	0
DepthKnown_A	503894702	503753621	0	0
RvalidKnown_A	503894702	503753621	0	0
WreadyKnown_A	503894702	503753621	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	11380831	0	0
T1	1469	194	0	0
T2	1563	2	0	0
T3	929	2	0	0
T4	10082	1606	0	0
T5	26948	837	0	0
T6	25116	72	0	0
T7	7195	218	0	0
T8	31585	405	0	0
T9	128131	15670	0	0
T10	131477	63	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	503753621	0	0
T1	1469	1398	0	0
T2	1563	1467	0	0
T3	929	857	0	0
T4	10082	10010	0	0
T5	26948	26878	0	0
T6	25116	25038	0	0
T7	7195	7111	0	0
T8	31585	31519	0	0
T9	128131	128043	0	0
T10	131477	131413	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	503753621	0	0
T1	1469	1398	0	0
T2	1563	1467	0	0
T3	929	857	0	0
T4	10082	10010	0	0
T5	26948	26878	0	0
T6	25116	25038	0	0
T7	7195	7111	0	0
T8	31585	31519	0	0
T9	128131	128043	0	0
T10	131477	131413	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	503753621	0	0
T1	1469	1398	0	0
T2	1563	1467	0	0
T3	929	857	0	0
T4	10082	10010	0	0
T5	26948	26878	0	0
T6	25116	25038	0	0
T7	7195	7111	0	0
T8	31585	31519	0	0
T9	128131	128043	0	0
T10	131477	131413	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0