Unified Coverage Report :: Module :: spi_device_csr_assert_fpv

Module : spi_device_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_spi_device_csr_assert_0/spi_device_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.spi_device_csr_assert	100.00						100.00

---

Module Instance : tb.dut.spi_device_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.52	95.20	84.31	97.00		90.62	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : spi_device_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	58	58	100.00	58	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	58	58	100.00	58	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	503894702	4068	0	0
addr_swap_data_rd_A	503894702	1866	0	0
addr_swap_mask_rd_A	503894702	1836	0	0
cfg_rd_A	503894702	2381	0	0
cmd_filter_0_rd_A	503894702	9703	0	0
cmd_filter_1_rd_A	503894702	9518	0	0
cmd_filter_2_rd_A	503894702	10920	0	0
cmd_filter_3_rd_A	503894702	10160	0	0
cmd_filter_4_rd_A	503894702	9988	0	0
cmd_filter_5_rd_A	503894702	9661	0	0
cmd_filter_6_rd_A	503894702	9620	0	0
cmd_filter_7_rd_A	503894702	9511	0	0
cmd_info_0_rd_A	503894702	4910	0	0
cmd_info_10_rd_A	503894702	5066	0	0
cmd_info_11_rd_A	503894702	4825	0	0
cmd_info_12_rd_A	503894702	4675	0	0
cmd_info_13_rd_A	503894702	4100	0	0
cmd_info_14_rd_A	503894702	5239	0	0
cmd_info_15_rd_A	503894702	5142	0	0
cmd_info_16_rd_A	503894702	5192	0	0
cmd_info_17_rd_A	503894702	4962	0	0
cmd_info_18_rd_A	503894702	4717	0	0
cmd_info_19_rd_A	503894702	5028	0	0
cmd_info_1_rd_A	503894702	5245	0	0
cmd_info_20_rd_A	503894702	5025	0	0
cmd_info_21_rd_A	503894702	4637	0	0
cmd_info_22_rd_A	503894702	4867	0	0
cmd_info_23_rd_A	503894702	4457	0	0
cmd_info_2_rd_A	503894702	4543	0	0
cmd_info_3_rd_A	503894702	5242	0	0
cmd_info_4_rd_A	503894702	4488	0	0
cmd_info_5_rd_A	503894702	5077	0	0
cmd_info_6_rd_A	503894702	5021	0	0
cmd_info_7_rd_A	503894702	4888	0	0
cmd_info_8_rd_A	503894702	5034	0	0
cmd_info_9_rd_A	503894702	4660	0	0
cmd_info_en4b_rd_A	503894702	2166	0	0
cmd_info_ex4b_rd_A	503894702	2154	0	0
cmd_info_wrdi_rd_A	503894702	2143	0	0
cmd_info_wren_rd_A	503894702	2080	0	0
intercept_en_rd_A	503894702	2589	0	0
intr_enable_rd_A	503894702	4157	0	0
jedec_cc_rd_A	503894702	2123	0	0
jedec_id_rd_A	503894702	2165	0	0
mailbox_addr_rd_A	503894702	1872	0	0
payload_swap_data_rd_A	503894702	1919	0	0
payload_swap_mask_rd_A	503894702	1933	0	0
read_threshold_rd_A	503894702	2001	0	0
tpm_access_0_rd_A	503894702	2623	0	0
tpm_access_1_rd_A	503894702	1862	0	0
tpm_cfg_rd_A	503894702	2943	0	0
tpm_did_vid_rd_A	503894702	2177	0	0
tpm_int_enable_rd_A	503894702	1932	0	0
tpm_int_status_rd_A	503894702	1966	0	0
tpm_int_vector_rd_A	503894702	1927	0	0
tpm_intf_capability_rd_A	503894702	1980	0	0
tpm_rid_rd_A	503894702	1812	0	0
tpm_sts_rd_A	503894702	1935	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	4068	0	0
T104	4670	3	0	0
T105	20053	220	0	0
T106	13041	213	0	0
T130	14914	12	0	0
T131	4014	10	0	0
T132	23556	392	0	0
T133	19167	7	0	0
T138	14548	188	0	0
T143	2415	4	0	0
T144	11573	13	0	0

addr_swap_data_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	1866	0	0
T104	4670	5	0	0
T130	14914	10	0	0
T152	3917	7	0	0
T158	79210	151	0	0
T180	4853	5	0	0
T181	10812	21	0	0
T182	90927	257	0	0
T183	20874	64	0	0
T184	4153	4	0	0
T185	74800	74	0	0

addr_swap_mask_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	1836	0	0
T104	4670	13	0	0
T130	14914	17	0	0
T149	7107	5	0	0
T152	3917	1	0	0
T158	79210	130	0	0
T180	4853	6	0	0
T181	10812	17	0	0
T182	90927	260	0	0
T183	20874	56	0	0
T184	4153	1	0	0

cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	2381	0	0
T104	4670	13	0	0
T114	2195	2	0	0
T130	14914	9	0	0
T149	7107	1	0	0
T152	3917	7	0	0
T158	79210	116	0	0
T180	4853	10	0	0
T181	10812	15	0	0
T182	90927	254	0	0
T183	20874	67	0	0

cmd_filter_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	9703	0	0
T104	4670	145	0	0
T114	2195	4	0	0
T130	14914	135	0	0
T149	7107	81	0	0
T152	3917	6	0	0
T158	79210	148	0	0
T180	4853	118	0	0
T181	10812	17	0	0
T182	90927	231	0	0
T186	4052	66	0	0

cmd_filter_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	9518	0	0
T104	4670	6	0	0
T114	2195	4	0	0
T130	14914	102	0	0
T149	7107	63	0	0
T152	3917	123	0	0
T158	79210	107	0	0
T180	4853	9	0	0
T181	10812	158	0	0
T182	90927	268	0	0
T186	4052	59	0	0

cmd_filter_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	10920	0	0
T104	4670	17	0	0
T130	14914	196	0	0
T149	7107	86	0	0
T152	3917	109	0	0
T158	79210	133	0	0
T180	4853	1	0	0
T181	10812	153	0	0
T182	90927	219	0	0
T183	20874	32	0	0
T186	4052	76	0	0

cmd_filter_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	10160	0	0
T104	4670	143	0	0
T130	14914	108	0	0
T149	7107	73	0	0
T152	3917	9	0	0
T158	79210	132	0	0
T180	4853	114	0	0
T181	10812	286	0	0
T182	90927	223	0	0
T183	20874	44	0	0
T184	4153	112	0	0

cmd_filter_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	9988	0	0
T104	4670	13	0	0
T114	2195	10	0	0
T130	14914	152	0	0
T149	7107	2	0	0
T152	3917	4	0	0
T158	79210	143	0	0
T180	4853	1	0	0
T181	10812	133	0	0
T182	90927	212	0	0
T186	4052	101	0	0

cmd_filter_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	9661	0	0
T104	4670	8	0	0
T130	14914	174	0	0
T149	7107	115	0	0
T152	3917	93	0	0
T158	79210	164	0	0
T180	4853	137	0	0
T181	10812	288	0	0
T182	90927	183	0	0
T183	20874	57	0	0
T187	7257	7	0	0

cmd_filter_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	9620	0	0
T104	4670	4	0	0
T114	2195	7	0	0
T130	14914	7	0	0
T149	7107	63	0	0
T158	79210	144	0	0
T180	4853	119	0	0
T181	10812	144	0	0
T182	90927	223	0	0
T183	20874	90	0	0
T186	4052	9	0	0

cmd_filter_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	9511	0	0
T104	4670	13	0	0
T114	2195	3	0	0
T130	14914	114	0	0
T149	7107	78	0	0
T152	3917	6	0	0
T158	79210	142	0	0
T180	4853	8	0	0
T181	10812	124	0	0
T182	90927	247	0	0
T188	10547	7	0	0

cmd_info_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	4910	0	0
T104	4670	8	0	0
T130	14914	65	0	0
T149	7107	19	0	0
T152	3917	45	0	0
T158	79210	121	0	0
T180	4853	1	0	0
T181	10812	75	0	0
T182	90927	200	0	0
T183	20874	87	0	0
T184	4153	4	0	0

cmd_info_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	5066	0	0
T104	4670	4	0	0
T130	14914	35	0	0
T149	7107	69	0	0
T152	3917	41	0	0
T158	79210	140	0	0
T180	4853	47	0	0
T181	10812	17	0	0
T182	90927	253	0	0
T183	20874	53	0	0
T186	4052	19	0	0

cmd_info_11_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	4825	0	0
T104	4670	13	0	0
T114	2195	7	0	0
T130	14914	15	0	0
T149	7107	94	0	0
T152	3917	2	0	0
T158	79210	163	0	0
T180	4853	6	0	0
T181	10812	4	0	0
T182	90927	189	0	0
T183	20874	94	0	0

cmd_info_12_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	4675	0	0
T104	4670	53	0	0
T114	2195	6	0	0
T130	14914	78	0	0
T149	7107	25	0	0
T152	3917	6	0	0
T158	79210	141	0	0
T180	4853	48	0	0
T181	10812	4	0	0
T182	90927	197	0	0
T188	10547	2	0	0

cmd_info_13_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	4100	0	0
T104	4670	14	0	0
T114	2195	4	0	0
T130	14914	52	0	0
T158	79210	106	0	0
T180	4853	2	0	0
T181	10812	104	0	0
T182	90927	199	0	0
T183	20874	57	0	0
T184	4153	48	0	0
T186	4052	55	0	0

cmd_info_14_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	5239	0	0
T104	4670	8	0	0
T130	14914	90	0	0
T149	7107	35	0	0
T152	3917	7	0	0
T158	79210	138	0	0
T180	4853	7	0	0
T181	10812	22	0	0
T182	90927	226	0	0
T183	20874	41	0	0
T186	4052	29	0	0

cmd_info_15_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	5142	0	0
T104	4670	83	0	0
T130	14914	83	0	0
T149	7107	37	0	0
T152	3917	30	0	0
T158	79210	116	0	0
T180	4853	7	0	0
T181	10812	75	0	0
T182	90927	243	0	0
T183	20874	73	0	0
T186	4052	1	0	0

cmd_info_16_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	5192	0	0
T104	4670	8	0	0
T130	14914	24	0	0
T149	7107	56	0	0
T152	3917	46	0	0
T158	79210	126	0	0
T180	4853	56	0	0
T181	10812	69	0	0
T182	90927	233	0	0
T183	20874	49	0	0
T186	4052	41	0	0

cmd_info_17_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	4962	0	0
T104	4670	17	0	0
T114	2195	6	0	0
T130	14914	93	0	0
T149	7107	3	0	0
T152	3917	39	0	0
T158	79210	158	0	0
T180	4853	7	0	0
T181	10812	109	0	0
T182	90927	192	0	0
T183	20874	38	0	0

cmd_info_18_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	4717	0	0
T104	4670	12	0	0
T130	14914	40	0	0
T149	7107	7	0	0
T152	3917	42	0	0
T158	79210	124	0	0
T180	4853	49	0	0
T181	10812	60	0	0
T182	90927	203	0	0
T183	20874	42	0	0
T184	4153	5	0	0

cmd_info_19_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	5028	0	0
T130	14914	40	0	0
T149	7107	68	0	0
T152	3917	3	0	0
T158	79210	113	0	0
T180	4853	50	0	0
T181	10812	19	0	0
T182	90927	226	0	0
T183	20874	29	0	0
T184	4153	56	0	0
T186	4052	34	0	0

cmd_info_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	5245	0	0
T104	4670	11	0	0
T114	2195	1	0	0
T130	14914	41	0	0
T149	7107	25	0	0
T152	3917	37	0	0
T158	79210	157	0	0
T180	4853	74	0	0
T181	10812	67	0	0
T182	90927	220	0	0
T183	20874	40	0	0

cmd_info_20_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	5025	0	0
T104	4670	4	0	0
T130	14914	41	0	0
T149	7107	47	0	0
T152	3917	58	0	0
T158	79210	151	0	0
T180	4853	31	0	0
T181	10812	128	0	0
T182	90927	223	0	0
T183	20874	38	0	0
T186	4052	29	0	0

cmd_info_21_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	4637	0	0
T104	4670	10	0	0
T130	14914	27	0	0
T149	7107	31	0	0
T152	3917	31	0	0
T158	79210	155	0	0
T180	4853	46	0	0
T181	10812	79	0	0
T182	90927	233	0	0
T183	20874	98	0	0
T186	4052	6	0	0

cmd_info_22_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	4867	0	0
T104	4670	11	0	0
T114	2195	3	0	0
T130	14914	47	0	0
T149	7107	27	0	0
T158	79210	110	0	0
T180	4853	5	0	0
T181	10812	46	0	0
T182	90927	282	0	0
T183	20874	86	0	0
T186	4052	1	0	0

cmd_info_23_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	4457	0	0
T104	4670	54	0	0
T114	2195	2	0	0
T130	14914	36	0	0
T149	7107	25	0	0
T152	3917	33	0	0
T158	79210	131	0	0
T180	4853	2	0	0
T181	10812	44	0	0
T182	90927	174	0	0
T186	4052	15	0	0

cmd_info_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	4543	0	0
T104	4670	8	0	0
T114	2195	1	0	0
T130	14914	24	0	0
T152	3917	4	0	0
T158	79210	131	0	0
T180	4853	80	0	0
T181	10812	59	0	0
T182	90927	253	0	0
T183	20874	50	0	0
T186	4052	35	0	0

cmd_info_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	5242	0	0
T104	4670	73	0	0
T130	14914	84	0	0
T149	7107	43	0	0
T158	79210	118	0	0
T180	4853	6	0	0
T181	10812	57	0	0
T182	90927	213	0	0
T183	20874	44	0	0
T184	4153	63	0	0
T186	4052	36	0	0

cmd_info_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	4488	0	0
T104	4670	2	0	0
T130	14914	31	0	0
T149	7107	19	0	0
T152	3917	36	0	0
T158	79210	142	0	0
T180	4853	61	0	0
T181	10812	104	0	0
T182	90927	202	0	0
T183	20874	48	0	0
T184	4153	43	0	0

cmd_info_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	5077	0	0
T104	4670	41	0	0
T130	14914	60	0	0
T149	7107	18	0	0
T152	3917	7	0	0
T158	79210	124	0	0
T180	4853	3	0	0
T181	10812	22	0	0
T182	90927	196	0	0
T183	20874	67	0	0
T186	4052	2	0	0

cmd_info_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	5021	0	0
T104	4670	69	0	0
T130	14914	48	0	0
T149	7107	8	0	0
T152	3917	52	0	0
T158	79210	154	0	0
T180	4853	35	0	0
T181	10812	62	0	0
T182	90927	248	0	0
T183	20874	53	0	0
T186	4052	5	0	0

cmd_info_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	4888	0	0
T104	4670	12	0	0
T114	2195	9	0	0
T130	14914	18	0	0
T149	7107	27	0	0
T152	3917	7	0	0
T158	79210	140	0	0
T180	4853	4	0	0
T181	10812	111	0	0
T182	90927	202	0	0
T183	20874	80	0	0

cmd_info_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	5034	0	0
T104	4670	61	0	0
T114	2195	4	0	0
T130	14914	78	0	0
T149	7107	35	0	0
T152	3917	2	0	0
T158	79210	138	0	0
T180	4853	36	0	0
T181	10812	57	0	0
T182	90927	215	0	0
T186	4052	5	0	0

cmd_info_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	4660	0	0
T104	4670	3	0	0
T114	2195	5	0	0
T130	14914	50	0	0
T149	7107	39	0	0
T152	3917	37	0	0
T158	79210	116	0	0
T180	4853	46	0	0
T181	10812	18	0	0
T182	90927	194	0	0
T188	10547	6	0	0

cmd_info_en4b_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	2166	0	0
T104	4670	9	0	0
T114	2195	1	0	0
T130	14914	2	0	0
T149	7107	10	0	0
T152	3917	4	0	0
T158	79210	129	0	0
T180	4853	5	0	0
T181	10812	26	0	0
T182	90927	215	0	0
T183	20874	98	0	0

cmd_info_ex4b_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	2154	0	0
T104	4670	10	0	0
T130	14914	10	0	0
T152	3917	11	0	0
T158	79210	138	0	0
T180	4853	5	0	0
T181	10812	28	0	0
T182	90927	222	0	0
T183	20874	66	0	0
T184	4153	4	0	0
T186	4052	1	0	0

cmd_info_wrdi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	2143	0	0
T130	14914	8	0	0
T149	7107	12	0	0
T152	3917	9	0	0
T158	79210	127	0	0
T180	4853	2	0	0
T181	10812	22	0	0
T182	90927	259	0	0
T183	20874	71	0	0
T186	4052	15	0	0
T188	10547	6	0	0

cmd_info_wren_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	2080	0	0
T104	4670	10	0	0
T130	14914	24	0	0
T149	7107	9	0	0
T152	3917	3	0	0
T158	79210	129	0	0
T181	10812	10	0	0
T182	90927	241	0	0
T183	20874	27	0	0
T184	4153	10	0	0
T186	4052	6	0	0

intercept_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	2589	0	0
T104	4670	8	0	0
T130	14914	28	0	0
T149	7107	9	0	0
T152	3917	11	0	0
T158	79210	115	0	0
T180	4853	8	0	0
T181	10812	23	0	0
T182	90927	223	0	0
T183	20874	98	0	0
T186	4052	3	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	4157	0	0
T35	230980	46	0	0
T36	4470	0	0	0
T69	105777	0	0	0
T172	0	28	0	0
T189	0	30	0	0
T190	0	18	0	0
T191	0	34	0	0
T192	0	9	0	0
T193	0	3	0	0
T194	0	14	0	0
T195	0	29	0	0
T196	0	26	0	0
T197	955548	0	0	0
T198	915	0	0	0
T199	1384	0	0	0
T200	291310	0	0	0
T201	592621	0	0	0
T202	261135	0	0	0
T203	5864	0	0	0

jedec_cc_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	2123	0	0
T104	4670	7	0	0
T114	2195	6	0	0
T130	14914	9	0	0
T149	7107	12	0	0
T152	3917	3	0	0
T158	79210	138	0	0
T180	4853	8	0	0
T181	10812	15	0	0
T182	90927	198	0	0
T186	4052	7	0	0

jedec_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	2165	0	0
T104	4670	11	0	0
T130	14914	17	0	0
T152	3917	2	0	0
T158	79210	119	0	0
T180	4853	13	0	0
T181	10812	22	0	0
T182	90927	230	0	0
T183	20874	66	0	0
T184	4153	9	0	0
T186	4052	6	0	0

mailbox_addr_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	1872	0	0
T104	4670	11	0	0
T130	14914	2	0	0
T149	7107	2	0	0
T152	3917	2	0	0
T158	79210	152	0	0
T180	4853	6	0	0
T181	10812	17	0	0
T182	90927	230	0	0
T183	20874	47	0	0
T184	4153	6	0	0

payload_swap_data_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	1919	0	0
T104	4670	14	0	0
T114	2195	2	0	0
T130	14914	27	0	0
T149	7107	3	0	0
T152	3917	2	0	0
T158	79210	154	0	0
T180	4853	1	0	0
T181	10812	7	0	0
T182	90927	230	0	0
T183	20874	47	0	0

payload_swap_mask_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	1933	0	0
T104	4670	4	0	0
T114	2195	1	0	0
T130	14914	27	0	0
T158	79210	158	0	0
T180	4853	4	0	0
T181	10812	18	0	0
T182	90927	219	0	0
T183	20874	24	0	0
T184	4153	1	0	0
T186	4052	7	0	0

read_threshold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	2001	0	0
T104	4670	5	0	0
T114	2195	2	0	0
T130	14914	15	0	0
T149	7107	2	0	0
T152	3917	4	0	0
T158	79210	125	0	0
T180	4853	1	0	0
T181	10812	16	0	0
T182	90927	227	0	0
T186	4052	3	0	0

tpm_access_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	2623	0	0
T104	4670	22	0	0
T130	14914	27	0	0
T149	7107	5	0	0
T152	3917	12	0	0
T158	79210	109	0	0
T180	4853	7	0	0
T181	10812	43	0	0
T182	90927	218	0	0
T183	20874	45	0	0
T186	4052	6	0	0

tpm_access_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	1862	0	0
T104	4670	6	0	0
T130	14914	12	0	0
T149	7107	3	0	0
T158	79210	117	0	0
T180	4853	5	0	0
T181	10812	8	0	0
T182	90927	232	0	0
T183	20874	82	0	0
T184	4153	4	0	0
T185	74800	65	0	0

tpm_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	2943	0	0
T104	4670	9	0	0
T130	14914	30	0	0
T149	7107	21	0	0
T152	3917	5	0	0
T158	79210	124	0	0
T180	4853	26	0	0
T181	10812	44	0	0
T182	90927	202	0	0
T183	20874	95	0	0
T186	4052	6	0	0

tpm_did_vid_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	2177	0	0
T104	4670	12	0	0
T130	14914	12	0	0
T149	7107	2	0	0
T158	79210	119	0	0
T180	4853	9	0	0
T181	10812	24	0	0
T182	90927	252	0	0
T183	20874	54	0	0
T184	4153	9	0	0
T186	4052	12	0	0

tpm_int_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	1932	0	0
T104	4670	12	0	0
T114	2195	3	0	0
T130	14914	18	0	0
T149	7107	16	0	0
T152	3917	2	0	0
T158	79210	135	0	0
T181	10812	16	0	0
T182	90927	221	0	0
T183	20874	91	0	0
T184	4153	5	0	0

tpm_int_status_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	1966	0	0
T104	4670	5	0	0
T114	2195	3	0	0
T130	14914	16	0	0
T152	3917	2	0	0
T158	79210	134	0	0
T180	4853	6	0	0
T181	10812	9	0	0
T182	90927	233	0	0
T183	20874	119	0	0
T184	4153	1	0	0

tpm_int_vector_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	1927	0	0
T104	4670	13	0	0
T114	2195	6	0	0
T130	14914	5	0	0
T149	7107	4	0	0
T152	3917	5	0	0
T158	79210	135	0	0
T180	4853	6	0	0
T181	10812	14	0	0
T182	90927	230	0	0
T186	4052	1	0	0

tpm_intf_capability_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	1980	0	0
T104	4670	10	0	0
T114	2195	4	0	0
T130	14914	4	0	0
T149	7107	7	0	0
T152	3917	6	0	0
T158	79210	145	0	0
T180	4853	3	0	0
T181	10812	26	0	0
T182	90927	205	0	0
T183	20874	74	0	0

tpm_rid_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	1812	0	0
T104	4670	7	0	0
T114	2195	4	0	0
T130	14914	18	0	0
T149	7107	1	0	0
T152	3917	8	0	0
T158	79210	114	0	0
T180	4853	2	0	0
T181	10812	17	0	0
T182	90927	201	0	0
T186	4052	6	0	0

tpm_sts_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503894702	1935	0	0
T104	4670	7	0	0
T130	14914	5	0	0
T158	79210	181	0	0
T180	4853	1	0	0
T181	10812	23	0	0
T182	90927	218	0	0
T183	20874	103	0	0
T184	4153	7	0	0
T185	74800	86	0	0
T204	15223	23	0	0